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Mixed Signal Design Verification Engineer

A global leader in wireless technology innovation and semiconductor development, specializing in 5G, AI/ML, compute, IoT, and automotive solutions.
$140,000 - $210,000
Backend
Mid-Level Software Engineer
In-Person
5,000+ Employees
2+ years of experience
AI · Automotive · Enterprise SaaS

Description For Mixed Signal Design Verification Engineer

Join Qualcomm's prestigious design verification team in a role that sits at the intersection of digital and analog engineering. As a Mixed Signal Design Verification Engineer, you'll be responsible for verifying high-speed mixed-signal IP designs crucial for cutting-edge technologies in 5G, AI/ML, compute, IoT, and automotive applications.

The position offers a unique opportunity to work with advanced verification methodologies and tools, handling everything from system-level concepts to tape out and post-silicon support. You'll be working with state-of-the-art technologies including PCIe, USB, MIPI, CXL, and various other protocols, while collaborating with cross-functional teams across digital design, analog circuit design, and SoC integration.

Qualcomm offers an exceptional compensation package, including a competitive base salary range of $140,000 to $210,000, annual discretionary bonuses, and RSU grants. The company's comprehensive benefits package supports employees' success at work, at home, and in their personal development.

The role requires a strong technical foundation with at least 2 years of ASIC design verification experience and expertise in SystemVerilog/UVM. You'll be joining a global technology leader known for pushing the boundaries of wireless technology and semiconductor innovation. The position offers significant growth opportunities, working alongside industry experts and contributing to world-changing innovations.

This is an ideal opportunity for a verification engineer looking to work on cutting-edge mixed-signal designs while being part of a company that values innovation, professional growth, and work-life balance. The role combines technical challenges with the opportunity to impact next-generation technology solutions across multiple domains.

Last updated 6 days ago

Responsibilities For Mixed Signal Design Verification Engineer

  • Define pre-silicon and post-silicon testplans based on design specs
  • Architect and develop testbench using SystemVerilog/UVM
  • Author assertions in SVA, develop testcases, coverage models
  • Work with digital design, analog circuit design, and SoC integration teams
  • Complete PHY level verification and integration into subsystem and SoC

Requirements For Mixed Signal Design Verification Engineer

Python
Java
  • Master's/Bachelor's degree in Electrical Engineering, Computer Engineering, or related field
  • 2+ years ASIC design verification experience
  • Knowledge of SystemVerilog/UVM
  • Experience with ASIC simulation/formal tools
  • Experience in scripting languages (Python or Perl) preferred
  • Knowledge of standard protocols (PCIe, USB, MIPI, LPDDR) preferred

Benefits For Mixed Signal Design Verification Engineer

401k
Medical Insurance
Vision Insurance
Dental Insurance
Mental Health Assistance
  • Competitive annual discretionary bonus
  • RSU grants
  • Tuition reimbursement
  • Mentorship programs
  • Comprehensive benefits package

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