RTL Design- Sr Engineer
Description For RTL Design- Sr Engineer
Qualcomm India Private Limited is seeking an experienced RTL Design Senior Engineer for their Chennai location. This role requires expertise in Logic design, micro-architecture, and RTL coding, with hands-on experience in SoC design and integration for complex SoCs. The ideal candidate should have proficiency in Verilog/System-Verilog and knowledge of AMBA protocols, SoC clocking/reset/debug architecture, and peripherals like USB, PCIE, and SDCC.
Key responsibilities include:
- Developing RTL code for complex SoC designs
- Working on constraint development and timing closure
- Collaborating with SoC verification and validation teams for pre/post Silicon debug
- Implementing low power SoC designs
- Working on multi-clock designs and asynchronous interfaces
- Creating pad rings and working with chip-level floorplan teams
- Using ASIC development tools such as Lint, CDC, Design compiler, and Primetime
The role requires a Bachelor's or Master's degree in Computer Science, Electrical/Electronics Engineering, or a related field, with 3-6 years of relevant experience. Qualcomm offers a supportive and inclusive work environment, fostering innovation and providing opportunities for career growth. The company is committed to diversity, equity, and inclusion, and offers comprehensive benefits including health coverage, wealth-building programs, and wellbeing resources.
Join Qualcomm to work alongside leading engineering and technology experts, contribute to world-changing innovations, and unlock your full potential in a dynamic and rewarding career.
Responsibilities For RTL Design- Sr Engineer
- Develop RTL code for complex SoC designs
- Work on constraint development and timing closure
- Collaborate with SoC verification and validation teams for pre/post Silicon debug
- Implement low power SoC designs
- Work on multi-clock designs and asynchronous interfaces
- Create pad rings and work with chip-level floorplan teams
- Use ASIC development tools such as Lint, CDC, Design compiler, and Primetime
Requirements For RTL Design- Sr Engineer
- Bachelor's or Master's degree in Computer Science, Electrical/Electronics Engineering, or related field
- 3-6 years of experience in Hardware Engineering or related work
- Expertise in Logic design, micro-architecture, and RTL coding
- Hands-on experience with SoC design and integration for complex SoCs
- Proficiency in Verilog/System-Verilog
- Knowledge of AMBA protocols - AXI, AHB, APB
- Understanding of SoC clocking/reset/debug architecture and peripherals like USB, PCIE, and SDCC
- Experience in constraint development and timing closure
- Hands-on experience in low power SoC design
- Experience in Synthesis and understanding of timing concepts for ASIC
- Hands-on experience in Multi Clock designs and Asynchronous interface
- Experience with ASIC development tools such as Lint, CDC, Design compiler, and Primetime
Benefits For RTL Design- Sr Engineer
- World-class health coverage for employees and eligible dependents
- Financial programs to help build a secure future
- Self and family resources for emotional/mental strength and resilience
- Wellbeing programs to support work-life balance
- Continuous learning and development programs
- Tuition reimbursement
- Mentorship opportunities
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