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Verification Engineer Interview Experience

February 4, 2020
Positive ExperienceNo Offer

Process

The phone screening happened. I had two rounds of phone screening, and they went very well.

I am waiting for the onsite interview invitation. It was a good exposure.

They asked a wide variety of questions, including about my projects and academic experience. They mainly focused on basics.

Questions

Projects:

  • Verification methodologies
  • UVM SystemVerilog testbench

Computer Architecture:

  • MESI protocol
  • Cache

UVM Testbench:

  • Components
  • Constructs

Digital Design Questions:

  • FSM types and differences
  • Divide by 2 clock design and code
  • Basic gate-level designs

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Interview Statistics

The following metrics were computed from 13 interview experiences for the Intel Verification Engineer role in United States.

Success Rate

46%
Pass Rate

Intel's interview process for their Verification Engineer roles in the United States is fairly selective, failing a large portion of engineers who go through it.

Experience Rating

Positive62%
Neutral38%
Negative0%

Candidates reported having very good feelings for Intel's Verification Engineer interview process in United States.

Intel Work Experiences