The entire process took about a month. Two phone interviews followed by an onsite interview. Environment was very friendly. Basics of Comp. Arch., Perl, Verilog and OOPs asked.
Virtual memory management is a key concept.
The following metrics were computed from 2 interview experiences for the Marvell Technology ASIC Verification Engineer role in Santa Clara, California.
Marvell Technology's interview process for their ASIC Verification Engineer roles in Santa Clara, California is fairly selective, failing a large portion of engineers who go through it.
Candidates reported having very good feelings for Marvell Technology's ASIC Verification Engineer interview process in Santa Clara, California.