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ASIC Verification Engineer Interview Experience - Santa Clara, California

December 1, 2013
Positive ExperienceGot Offer

Process

The entire process took about a month. Two phone interviews followed by an onsite interview. Environment was very friendly. Basics of Comp. Arch., Perl, Verilog and OOPs asked.

Questions

Virtual memory management is a key concept.

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Interview Statistics

The following metrics were computed from 2 interview experiences for the Marvell Technology ASIC Verification Engineer role in Santa Clara, California.

Success Rate

50%
Pass Rate

Marvell Technology's interview process for their ASIC Verification Engineer roles in Santa Clara, California is fairly selective, failing a large portion of engineers who go through it.

Experience Rating

Positive100%
Neutral0%
Negative0%

Candidates reported having very good feelings for Marvell Technology's ASIC Verification Engineer interview process in Santa Clara, California.

Marvell Technology Work Experiences