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Verification Engineer

Annapurna Labs, part of Amazon Web Services (AWS), develops innovative hardware and software for AWS cloud customers.
Embedded
Senior Software Engineer
In-Person
5,000+ Employees
5+ years of experience
Enterprise SaaS
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Description For Verification Engineer

AWS Utility Computing (UC) provides foundational services like Amazon S3 and EC2, continuously innovating in cloud technology. Within AWS UC, Annapurna Labs develops cutting-edge hardware and software solutions for AWS cloud customers. This role is part of the Pre-silicon Verification team, working on semiconductor platform development with revolutionary architecture.

As a Verification Engineer, you'll be responsible for ensuring the quality and reliability of hardware designs through comprehensive verification processes. The position requires expertise in RTL verification, hardware verification concepts, and programming skills. You'll work with advanced tools and methodologies like UVM and Coverage Driven verification to validate complex semiconductor designs.

The role offers the opportunity to work with world-class engineers in a dynamic, start-up-like environment within AWS. You'll be contributing to technologies that power the world's largest cloud provider, making a direct impact on AWS's infrastructure and services. The position combines the excitement of hardware development with the scale and resources of Amazon.

Amazon offers excellent work-life harmony, fostering an inclusive team culture with various employee-led affinity groups. The company provides strong mentorship opportunities and career growth through knowledge-sharing and professional development resources. As part of AWS, you'll be at the forefront of cloud computing innovation, working on projects that directly influence the future of cloud infrastructure.

Last updated 24 days ago

Requirements For Verification Engineer

Python
  • Electrical/Computer Science engineer
  • 5+ years of experience with RTL verification
  • Knowledge of Hardware Verification concepts and tools (UVM, Coverage Driven verification)
  • Sound understanding and knowledge of object-oriented programming concepts
  • Verilog/SystemVerilog/Specman experience

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