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Design Verification Engineer

A leading technology company that designs and develops consumer electronics, software, and services.
$175,800 - $312,200
Embedded
Senior Software Engineer
In-Person
5,000+ Employees
10+ years of experience
Hardware

Description For Design Verification Engineer

At Apple, we work every single day to craft products that enrich people's lives. As a Design Verification Engineer, you'll join our Hardware team to work on challenges that no one has solved yet. This role focuses on pre-silicon verification for IP designs, ensuring fully functional first silicon through comprehensive testing and verification processes.

You'll be responsible for establishing DV methodology, developing test plans, creating verification environments, and ensuring bug-free silicon delivery. The role involves working with cutting-edge hardware designs and requires expertise in SystemVerilog, UVM, and verification methodologies.

Apple offers a competitive compensation package with a base salary range of $175,800 to $312,200, plus additional benefits including stock options, comprehensive healthcare, and education reimbursement. You'll be working at our Cupertino headquarters, contributing to products that impact millions of users worldwide.

The ideal candidate brings 10+ years of experience, strong technical skills in verification methodologies, and expertise in scripting languages. You'll work with state-of-the-art tools and technologies while collaborating with world-class engineers to deliver excellence in hardware design verification.

Join Apple's Hardware team and be part of creating the next generation of innovative products that delight and inspire users worldwide. Your work will directly impact the quality and reliability of Apple's hardware products, making this an exceptional opportunity for a seasoned verification engineer looking to make a significant impact.

Last updated 16 hours ago

Responsibilities For Design Verification Engineer

  • Ensure bug-free first silicon for part of the SoC / IP
  • Develop detailed test and coverage plans based on micro-architecture
  • Develop verification methodology and environment
  • Execute verification plans including design bring-up
  • Track and report DV progress using various metrics

Requirements For Design Verification Engineer

Python
  • BS degree in technical subject area with minimum 10 years of proven experience
  • Solid knowledge of OOP, SystemVerilog, and UVM
  • Solid knowledge in developing scalable and portable test-benches
  • Experience with verification methodologies and tools
  • Excellent knowledge of scripting languages such as Python, Perl, TCL

Benefits For Design Verification Engineer

Medical Insurance
Dental Insurance
Vision Insurance
401k
Education Budget
Equity
Relocation Benefits
  • Comprehensive medical and dental coverage
  • Retirement benefits
  • Discounted products and free services
  • Education reimbursement
  • Stock options and employee stock purchase plan
  • Discretionary bonuses
  • Relocation assistance

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