Emulation Verification Engineer
Description For Emulation Verification Engineer
Apple is seeking an experienced Emulation Verification Engineer to join their hardware team in Cupertino. This role is critical in using Emulation for verification of large SoCs, working at the intersection of hardware design and verification.
As a member of the Emulation verification team, you'll play a key role in porting designs onto the Palladium platform and completing detailed Emulation testplans. You'll collaborate closely with Architecture, Design, DV, Silicon Validation, Power and SW teams to bring up large SoCs on the emulation platform.
The position requires expertise in synthesizable SystemVerilog/Verilog code, verification environments, and debugging skills. You'll be responsible for developing and applying synthesizable monitors/checkers, creating test plans, performing low power testing, and developing random stimulus infrastructure.
Apple offers a comprehensive compensation package including a base salary range of $175,800 to $312,200, plus equity opportunities through stock programs. Benefits include comprehensive medical/dental coverage, retirement benefits, education reimbursement, and various discounted products and services.
This is an opportunity to work on cutting-edge hardware verification at one of the world's leading technology companies, contributing to products that impact millions of users. The role offers significant technical challenges and the chance to work with multiple teams across Apple's hardware organization.
Responsibilities For Emulation Verification Engineer
- Collaborate with Architecture, Design, DV, Silicon Validation, Power and SW teams
- Develop/apply synthesizable monitors/checkers, stimulus on emulation platform
- Prepare and complete test plans and perform reviews
- Perform low power testing on emulation platform
- Develop code for Design and verification using Verilog/System Verilog/UVM
- Develop random stimulus infrastructure by reusing existing UVM simulation constraints
Requirements For Emulation Verification Engineer
- Minimum of BS + 10 years relevant industry experience
- Understanding of the tool flow from RTL to Emulation
- Good understanding of any Standard Emulator or FPGA flow
- Experience in writing Synthesize-able SystemVerilog/Verilog code
- Experience with System Verilog verification environments
- Experience with writing and debugging test FW
- Experience on any Scripting (Perl/Python/TCL)
- Excellent analytical and debug skills
Benefits For Emulation Verification Engineer
- Medical Insurance
- Dental Insurance
- Vision Insurance
- 401k
- Education Budget
- Equity
