FE Design and Timing Analysis Engineer
Description For FE Design and Timing Analysis Engineer
Come and join Apple's growing wireless silicon development team. Our wireless SoC organization is responsible for all aspects of wireless silicon development, emphasizing highly energy-efficient design and new technologies that transform the user experience at the product level. All of this is driven by a world-class vertically integrated engineering team spanning RF/Analog architecture and design, Systems/PHY/MAC architecture and design, VLSI/RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW engineering.
As a Front End and Timing Analysis Engineer, you will be involved with all phases of implementing high performance, low power wireless SoCs from RTL to delivery of our final GDSII. Your responsibilities include:
- Generate chip or block level static timing constraints
- Synthesize design with UPF/DFT/BIST
- Close timing on critical blocks by working with design and PD teams
- Perform timing optimization and implement the design for functionality
- Generate and implement functional ECOs
- Run static timing analysis flows at chip/block level and provide guidelines to fix violations to other designers
- Participate in establishing/improving CAD and design flow methodologies
- Work with multi-disciplinary groups to ensure timely delivery of high-quality designs
This role offers an exciting opportunity to work on cutting-edge wireless technology in a fast-paced and challenging environment. You'll collaborate with people across different functional areas and thrive during crisis times. If you're passionate about pushing the boundaries of wireless silicon development and want to be part of a team that transforms user experiences, this role at Apple is perfect for you.
Apple offers a competitive compensation package, including base pay, potential stock awards, and comprehensive benefits. You'll have the opportunity to grow your skills, advance your career, and contribute to groundbreaking products that millions of people use every day.
Responsibilities For FE Design and Timing Analysis Engineer
- Generate chip or block level static timing constraints
- Synthesize design with UPF/DFT/BIST
- Close timing on critical blocks by working with design and PD teams
- Perform timing optimization and implement the design for functionality
- Generate and implement functional ECOs
- Run static timing analysis flows at chip/block level and provide guidelines to fix violations
- Participate in establishing/improving CAD and design flow methodologies
- Work with multi-disciplinary groups to ensure timely delivery of high-quality designs
Requirements For FE Design and Timing Analysis Engineer
- Bachelors and 10+ years of relevant industry experience
- Knowledge of the ASIC design flow, synthesis, static timing analysis, RTL to Post Synthesis netlist
- Exposure to industry standard Timing, Logic Equivalence, Physical Design and Synthesis tools
- Proficient in scripting in TCL, Perl or Python
- Knowledge of basic SoC Architecture and HDL languages like Verilog / System Verilog
Benefits For FE Design and Timing Analysis Engineer
- Comprehensive medical and dental coverage
- Retirement benefits
- Discounted products and free services
- Education reimbursement for career advancement
- Discretionary restricted stock unit awards
- Employee Stock Purchase Plan
- Potential discretionary bonuses
- Potential relocation assistance
