FE Design and Timing Analysis Integration Engineer

Come and join Apple's growing wireless silicon development team. Our wireless SoC organization is responsible for all aspects of wireless silicon development, emphasizing highly energy-efficient design and new technologies that transform the user experience at the product level. All of this is driven by a world-class vertically integrated engineering team spanning RF/Analog architecture and design, Systems/PHY/MAC architecture and design, VLSI/RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW engineering.

As a Front End and Timing Analysis Engineer, you will be involved with all phases of implementing high performance, low power wireless SoCs from RTL to delivery of our final GDSII. Your responsibilities include:

• Generate chip or block level static timing constraints
• Synthesize design with UPF/DFT/BIST
• Close timing on critical blocks by working with design and PD teams
• Perform timing optimization and implement the design for functionality
• Generate and implement functional ECOs
• Run static timing analysis flows at chip/block level and provide guidelines to fix violations to other designers
• Participate in establishing/improving CAD and design flow methodologies
• Work with multi-disciplinary groups to ensure timely delivery of high-quality designs

If you enjoy a fast-paced and challenging environment, collaborate with people across different functional areas, and thrive during crisis times, we encourage you to apply. This role offers an opportunity to work on cutting-edge wireless technologies and contribute to Apple's innovative products.