RTL Design Engineer
Description For RTL Design Engineer
At Apple, we work every single day to craft products that enrich people's lives. As an RTL Design Engineer, you will join a dynamic group working on challenges that no one has solved yet. This role offers the rare opportunity to craft upcoming products that will impact millions of Apple's customers daily.
You will be responsible for specifying and micro-architecting digital blocks in advanced mixed-signal circuits, as well as RTL coding of these blocks. The role involves active participation in design verification and bring-up by writing assertions, debugging code, and collaborating with the design verification team. You'll also contribute to lab bring-up by writing test scripts, analyzing data, and proposing experiments.
This position combines deep technical expertise in mixed-signal concepts, RTL design fundamentals, and verification techniques with hands-on development work. You'll work with cutting-edge tools and technologies while contributing to Apple's next generation of innovative products.
The ideal candidate brings strong communication skills and deep knowledge across multiple domains including Verilog, System-Verilog, front-end tools, and algorithm development. This role offers the opportunity to work on challenging technical problems while being part of Apple's mission to create products that delight users worldwide.
Apple offers a comprehensive benefits package and is committed to inclusion and diversity, seeking to promote equal opportunity for all applicants regardless of background.
Responsibilities For RTL Design Engineer
- Specify and micro-architect digital blocks in advanced mixed-signal circuits
- RTL coding of specified blocks
- Participate in design verification and bring-up
- Write meaningful assertions and debug code
- Interact with design verification team
- Participate in lab bring-up
- Write test scripts and analyze lab data
- Propose and conduct experiments
Requirements For RTL Design Engineer
- BS degree in technical discipline with minimum 10 years of relevant experience
- Deep knowledge of mixed signal concepts
- Deep knowledge of RTL design fundamentals
- Deep knowledge of Verilog and System-Verilog
- Deep knowledge of front-end tools (Verilog simulators, linters, clock-domain crossing checkers)
- Deep knowledge of System-Verilog assertions, checkers, and other design verification techniques
- Deep knowledge of scripting languages
- Deep knowledge of Algorithm developments
- Strong communication and presentation skills
