Apple is seeking a Sr. RFIC - PLL Design Engineer to join their growing wireless silicon development team in Irvine, California. This role is part of the Wireless Radio team and will have a critical impact on getting Apple's state-of-the-art wireless connectivity solutions into hundreds of millions of products.
Key responsibilities include:
- Leading design of radio transceiver chains including analog PLLs, VCOs, digital PLLs, DCOs, LOGen, and chain of blocks in RX and TX for wireless connectivity products
- Driving radio KPI (power, area, performance) to meet product requirements
- Working with cross-functional teams to define radio features enabling wireless innovation
- Hands-on design contributions from concept to actual design, simulations, and extractions
- Overseeing floorplan layout and verification to ensure successful tape-out
- Collaborating with RFIC test engineers in bring-up, debug, and optimization of wireless connectivity chips
- Providing design versus silicon measurements correlation and compliance with specifications for volume production
The ideal candidate will have:
- 10+ years of RF/analog and mixed-signal design experience in cutting-edge RF CMOS design
- Direct experience in designing and bringing wireless transceivers into mass production
- Expertise in fractional N Synthesizers, Digital PLLs, Analog PLLs, and LO-Gen design
- Deep understanding of analog, mixed-signal, and RF circuit design
- Familiarity with various RF transceiver architectures and system specifications
- Experience with Cadence Virtuoso, Spectre RF, Matlab, and EM simulation tools
- Knowledge of mixed-signal mode verification methodology
This role offers a competitive base pay range of $166,600 to $296,300, along with additional benefits such as stock options, comprehensive medical and dental coverage, retirement benefits, and educational reimbursement opportunities.
Join Apple's innovative team and contribute to the development of cutting-edge wireless technology that impacts millions of users worldwide.