Wireless SOC Design Verification Engineer
Description For Wireless SOC Design Verification Engineer
Apple is seeking a Wireless SOC Design Verification Engineer to join their Hardware team in Sunnyvale. This role offers an exciting opportunity to work on complex SOC verification, integrating sophisticated IP level DV environments and implementing effective coverage-driven test cases.
The position involves working with state-of-the-art Wireless SOCs, where you'll be responsible for pre-silicon RTL verification at both block and top levels. You'll gain extensive knowledge of wireless protocols, firmware-hardware interactions, and multi-chip SOC debug architecture.
As part of the team, you'll:
- Work on verifying complex SOCs and implementing reusable UVM testbenches
- Collaborate with cross-functional teams to improve product experience
- Learn all aspects of large-scale SOC architecture and wireless protocols
- Handle power management verification and low-power methodologies
- Engage in coverage-driven verification planning and implementation
The role offers competitive compensation ($175,800 - $312,200) plus benefits including comprehensive medical/dental coverage, stock options, and education reimbursement. This is an excellent opportunity for an experienced verification engineer to work on cutting-edge wireless technology at one of the world's leading tech companies.
The ideal candidate will have 10+ years of relevant experience, strong knowledge of UVM/OVM methodology, and proven experience with ASIC/SOC verification. You should be comfortable working in a dynamic environment and possess excellent communication skills.
Responsibilities For Wireless SOC Design Verification Engineer
- Understand details of High Efficiency SOC Architecture
- Deliver on Power Management designs using low-power methodologies
- Build coverage driven verification plans from specifications
- Architect UVM based highly reusable test benches
- Achieve targeted coverage, work with design teams
- Work closely with DV methodology architects
Requirements For Wireless SOC Design Verification Engineer
- BS and a minimum of 10 years relevant industry experience
- Dedicated/hands-on ASIC & SOC DV experience
- Sophisticated knowledge of HVL methodology (UVM/OVM) with most recent experience in UVM
- Experience with formal verification is a plus
- Experience taping out large SOC systems with embedded processor cores
- Hands-on verification experience of PCIe, Bus Fabric, NOC, AHB, AXI
- In-depth knowledge of low power design, UPF integration, boot-up
- Excellent communication and problem-solving skills
Benefits For Wireless SOC Design Verification Engineer
- Medical Insurance
- Dental Insurance
- Vision Insurance
- 401k
- Education Budget
- Equity
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