SLD FPGA Verification Engineer III - Lunar Permanence
Description For SLD FPGA Verification Engineer III - Lunar Permanence
Blue Origin, a pioneering space company, is seeking a Senior FPGA Verification Engineer III for their Lunar Permanence business unit, which focuses on developing Blue Moon landers and related products. This role is crucial in their mission to enable millions of people to live and work in space for Earth's benefit.
The position involves working within the avionics, guidance, and navigation group, where you'll be responsible for verifying FPGA-based solutions. The role combines technical expertise with leadership skills to impact safe human spaceflight. You'll be part of a collaborative FPGA team developing high-reliability, safety-critical avionics solutions for the Human Landing System (HLS) vehicle.
Key responsibilities include performing UVM-based verification, creating comprehensive validation plans, developing testbenches, and generating certification reports. The ideal candidate should have extensive experience with FPGA/ASIC verification, RTL simulation tools, and System Verilog, along with expertise in testbench development and coverage analysis.
The position offers competitive compensation ranging from $116,323 to $177,657 depending on location, along with comprehensive benefits including medical, dental, vision insurance, 401(k) matching, and educational support. Blue Origin provides a unique opportunity to work on cutting-edge space technology while contributing to humanity's future in space.
The company culture emphasizes safety, collaboration, and inclusion, welcoming diverse perspectives and encouraging professional growth. This role represents an excellent opportunity for experienced engineers passionate about space exploration to make a significant impact in developing lunar landing systems and advancing space technology.
Responsibilities For SLD FPGA Verification Engineer III - Lunar Permanence
- Perform requirements-based verification of FPGAs using Universal Verification Methodology (UVM)
- Create comprehensive verification and validation plan
- Develop IP/subsystem/system level testbench and tests
- Document plans and procedures
- Write directed and random test cases
- Generate reports in support of certification of design
- Debug FPGA/ASIC hardware and assist with HW/SW integration
Requirements For SLD FPGA Verification Engineer III - Lunar Permanence
- BS/MS in Electrical Engineering, Computer Engineering or related field
- 5+ years experience verifying FPGAs or ASICSs
- Experience with RTL simulation tools
- In-depth knowledge of System Verilog and UVM
- Expertise in developing testbench environment
- Experience with predictive testbench components
- Experience with constrained random verification
- Experience with Register Abstraction Layer
- Must be a U.S. citizen, permanent resident, or granted asylum
- Knowledge of scripting languages (Python, Perl, TCL/Shell)
- Working knowledge of NPR 7150.2, DO-254
Benefits For SLD FPGA Verification Engineer III - Lunar Permanence
- Medical insurance
- Dental insurance
- Vision insurance
- Life insurance
- Paid parental leave
- Short and long-term disability
- 401(k) with company match up to 5%
- Education Support Program
- Up to 4 weeks paid time off
- 14 company-paid holidays
- Discretionary bonus
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