DFT Engineer
Description For DFT Engineer
Broadcom's ASIC Product Division is seeking an experienced DFT (Design for Testability) Engineer for their Shanghai location. This role combines software engineering with hardware design, requiring expertise in both domains. The position involves leading comprehensive DFT programs from initial specification through implementation and verification, ultimately ensuring successful product releases.
The role is deeply technical, requiring expertise in various aspects of SoC DFT activities within Broadcom's ASIC Products Division. Key responsibilities include DFT Architecture design, test insertion and verification, pattern generation, and coverage improvement. The position requires strong programming skills in languages like Python, Ruby, TCL, or C++, combining software development with hardware testing expertise.
The ideal candidate will work at the intersection of software and hardware, implementing complex test solutions for cutting-edge semiconductor products. They will be responsible for working with various teams globally, including physical design, STA teams, and direct customer interaction. The position offers exposure to advanced semiconductor technologies, working on solutions for 7nm and beyond.
This role presents an excellent opportunity for experienced engineers looking to work with advanced semiconductor technologies at a global leader in the industry. The position offers the chance to work on challenging technical problems, innovate new DFT solutions, and collaborate with cross-functional teams worldwide. The role requires a blend of technical expertise, problem-solving skills, and strong communication abilities.
The successful candidate will join a dynamic team working on cutting-edge semiconductor technologies, with opportunities to influence test methodologies and contribute to next-generation chip designs. This position is ideal for someone who enjoys combining software development with hardware testing and wants to work at the forefront of semiconductor technology.
Responsibilities For DFT Engineer
- Understanding Broadcom & customer DFT feature requirements & DPPM goals & defining appropriate DFT specifications for the ASIC
- Implementing DFT, including Scan, MBIST, TAP, LBIST, IO, SerDes and other I/P DFT integration
- Working closely with STA and DI Engineers design closure for test
- Generating, Verifying & Debugging Test vectors before tape release
- Validating & Debugging Test vectors on ATE during the silicon bring up phase
- Assisting with silicon failure analysis, diagnostics & yield improvement efforts
- Interfacing with the customer, physical design and test engineering/manufacturing teams located globally
- Working closely with I/P DFT engineers & other stakeholders
- Debugging customer returned parts on the ATE
- Innovating newer DFT solutions to solve testability problems in 7nm & beyond
- Automating DFT & Test Vector Generation flows
Requirements For DFT Engineer
- Strong DFT background (such as IO and Analog DFT, ATPG and/or Scan, BIST, and others)
- Scan Insertion and scan compression background (DFT Compiler, Mentor TestKompress, etc.)
- Well-versed in ATPG vector generation, simulation, and debugging
- Experience in Verilog coding, testbench generation & simulation
- Memory BIST insertion and verification experience
- Knowledge in IEEE1149.1 and IEEE1149.6
- Basic knowledge Test-STA and constraints
- Strong background on IEE1687, IJTAG, ICL and PDL
- Bachelors in Electrical/Electronic/Computer Engineering with 10+ years experience or Masters with 8+ years experience
- Solid knowledge in analog and digital circuit design
- Good understanding of Si processing
- Excellent problem solving, debug, root cause analysis and communication skills
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