Senior Engineer - Memory Design Validation
Description For Senior Engineer - Memory Design Validation
Broadcom, a leading global technology company specializing in semiconductor and infrastructure software solutions, is seeking a Senior Engineer for Memory Design Validation. This role focuses on advanced memory technologies, working with cutting-edge 2nm process technology and various memory types including SRAM, Multi-Ports, Register File, TCAM, and ROM memory compilers.
The position involves leading complex validation efforts for memory design, requiring deep expertise in transistor-level circuit behavior, signal integrity analysis, and advanced simulation techniques. You'll be responsible for performing critical analyses including EM/IR simulations, timing validations, and power modeling, while also developing automation scripts to enhance verification workflows.
This role is perfect for someone who combines strong technical expertise in memory design with leadership capabilities. You'll work with state-of-the-art tools like HSPICE, HSIM, and Cadence, while coordinating with cross-functional teams to execute comprehensive validation strategies.
The ideal candidate should have extensive experience in memory macro development, strong understanding of sub-nanometer process technologies, and excellent problem-solving abilities. This position offers the opportunity to work on cutting-edge technology at one of the world's leading semiconductor companies, making a direct impact on next-generation memory solutions.
Working at Broadcom's Bangalore facility, you'll be part of a global team pushing the boundaries of semiconductor technology. The company offers a collaborative environment where you can grow your expertise while working on challenging projects that shape the future of memory design.
Responsibilities For Senior Engineer - Memory Design Validation
- Lead Memory Design Validation of SRAM, Multi-Ports, Register File, TCAM, and ROM memory compilers
- Perform functional verification and resolve design discrepancies
- Conduct signal integrity analysis and propose solutions
- Perform transistor level simulations for Power Up and Lock up issues
- Execute EM/IR analysis/simulations and evaluate timing impact
- Validate timing and internal margins through transistor level simulations
- Perform QA and validation checks for timing and power models
- Develop automation scripts for verification flow
- Support silicon debugging and correlation to spice models
- Coordinate with memory design leads and managers on validation plans
Requirements For Senior Engineer - Memory Design Validation
- Strong expertise in memory macros development
- Strong understanding of transistor level circuit behavior and analysis
- Knowledge of layout challenges in sub-nanometer process technologies
- Understanding of signal integrity, EM/IR, and reliability analysis
- Knowledge of memory behavioral and physical models
- Understanding of DFT Schemes and chip level integration
- Proficiency in transistor level simulators and automation scripts
- Experience with Cadence schematic/layout editor tools
- Experience with HSPICE, HSIM, XA, FineSim, XARA, nWave tools
- Skill/Perl/Python Scripting experience
- Good communication and leadership skills
- Strong debugging and problem-solving abilities
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