Senior Engineer - Memory Design Validation
Description For Senior Engineer - Memory Design Validation
Broadcom, a leading global technology company specializing in semiconductor and infrastructure software solutions, is seeking a Senior Engineer for Memory Design Validation. This role is crucial in developing and validating memory solutions using cutting-edge 2nm process technologies. The position involves leading validation efforts for various memory types including SRAM, Multi-Ports, Register File, TCAM, and ROM memory compilers.
The role combines deep technical expertise in memory design with hands-on validation and verification work. You'll be responsible for performing complex analyses including signal integrity, EM/IR simulations, and transistor-level simulations to ensure robust memory designs. The position requires strong analytical skills and expertise with industry-standard tools like Cadence, HSPICE, and various simulation platforms.
This is an excellent opportunity for an experienced engineer who wants to work at the forefront of semiconductor technology. You'll be collaborating with memory design leads, modeling leads, and managers while having the chance to impact critical memory solutions used in various applications. The role offers the perfect blend of technical leadership and hands-on engineering work.
The ideal candidate will bring strong expertise in memory macro development, deep understanding of transistor-level circuit behavior, and experience with modern process technologies. You'll need to be proficient in automation and scripting, with the ability to develop and implement efficient validation workflows. Strong communication and leadership skills are essential as you'll be coordinating with various teams and stakeholders.
Working at Broadcom means joining a global leader in technology, with opportunities to work on cutting-edge projects and technologies. The company offers a collaborative environment where innovation is encouraged and technical excellence is valued.
Responsibilities For Senior Engineer - Memory Design Validation
- Lead Memory Design Validation of SRAM, Multi-Ports, Register File, TCAM, and ROM memory compilers
- Perform functional verification and resolve design discrepancies
- Conduct signal integrity analysis and propose solutions
- Perform transistor level simulations for Power Up and Lock up issues
- Execute EM/IR analysis/simulations and evaluate timing impact
- Validate timing and internal margins through transistor level simulations
- Perform QA and validation checks for timing and power models
- Develop automation scripts for verification flow
- Support silicon debugging and correlation to spice models
- Coordinate with memory design leads and managers on validation plans
Requirements For Senior Engineer - Memory Design Validation
- Strong expertise in memory macros development
- Strong understanding of transistor level circuit behavior and analysis
- Knowledge of layout challenges in sub-nanometer process technologies
- Understanding of signal integrity, EM/IR, and reliability analysis
- Knowledge of memory behavioral and physical models
- Understanding of DFT Schemes and chip level integration
- Proficiency in transistor level simulators and automation scripts
- Experience with Cadence schematic/layout editor tools
- Experience with HSPICE, HSIM, XA, FineSim, XARA, nWave tools
- Skill/Perl/Python Scripting experience
- Good communication and leadership skills
- Strong debugging and problem-solving abilities
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