Senior Engineer - Memory Design Validation
Description For Senior Engineer - Memory Design Validation
Broadcom, a leading global technology company specializing in semiconductor and infrastructure software solutions, is seeking a Senior Engineer for Memory Design Validation. This role is crucial in developing and validating memory solutions using cutting-edge 2nm process technologies. The position involves leading validation efforts for various memory types including SRAM, Multi-Ports, Register File, TCAM, and ROM memory compilers.
The role demands a deep understanding of transistor-level circuit behavior, signal integrity analysis, and extensive experience with industry-standard tools like Cadence, HSPICE, and various simulators. You'll be responsible for performing critical analyses including EM/IR simulations, timing validations, and power modeling, while also developing automation scripts to enhance verification workflows.
This is an excellent opportunity for an experienced engineer who combines strong technical expertise in memory design with leadership capabilities. You'll work with cross-functional teams, coordinating with memory design leads, modeling leads, and managers to define and execute validation strategies. The position offers the chance to work on next-generation semiconductor technologies while being part of a global technology leader.
The ideal candidate should possess not only technical proficiency but also strong communication and problem-solving skills. Experience with scripting languages like Python, Perl, or Skill is highly valued. This role provides an opportunity to work on challenging projects that push the boundaries of semiconductor technology while contributing to Broadcom's continued innovation in the field.
Responsibilities For Senior Engineer - Memory Design Validation
- Lead Memory Design Validation of SRAM, Multi-Ports, Register File, TCAM, and ROM memory compilers
- Perform functional verification and resolve design discrepancies
- Conduct signal integrity analysis and propose solutions
- Perform transistor level simulations for Power Up and Lock up issues
- Execute EM/IR analysis/simulations and evaluate timing impact
- Validate timing and internal margins through transistor level simulations
- Perform QA and validation checks for timing and power models
- Develop automation scripts for verification flow
- Support silicon debugging and correlation to spice models
- Coordinate with memory design leads and managers on validation plans
Requirements For Senior Engineer - Memory Design Validation
- Strong expertise in memory macros development
- Strong understanding of transistor level circuit behavior and analysis
- Knowledge of layout challenges in sub-nanometer process technologies
- Understanding of signal integrity, EM/IR, and reliability analysis
- Knowledge of memory behavioral and physical models
- Understanding of DFT Schemes and chip level integration
- Proficiency in transistor level simulators and automation scripts
- Experience with Cadence schematic/layout editor tools
- Experience with HSPICE, HSIM, XA, FineSim, XARA, nWave tools
- Experience in Skill/Perl/Python Scripting
- Good communication and leadership skills
- Strong debugging and problem-solving skills
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