Staff Engineer - Memory Design Validation
Description For Staff Engineer - Memory Design Validation
Broadcom, a global leader in semiconductor and infrastructure software solutions, is seeking a Staff Engineer for Memory Design Validation to join their team in Bangalore. This role focuses on leading memory design validation efforts for various memory types including SRAM, Multi-Ports, Register File, TCAM, and ROM memory compilers in cutting-edge 2nm process technologies.
The position requires deep expertise in memory macro development and transistor-level circuit behavior, combining both technical depth and leadership responsibilities. You'll be working with state-of-the-art technology, performing complex analyses including signal integrity, EM/IR simulations, and timing validations. The role involves collaboration with memory design leads, modeling leads, and managers to define and execute validation strategies.
This is an excellent opportunity for an experienced engineer who wants to work at the forefront of semiconductor technology. You'll be involved in critical aspects of memory design validation, from functional verification to silicon debugging. The position offers the chance to work with advanced tools and technologies while leading technical initiatives.
The ideal candidate should have strong expertise in memory macro development, deep understanding of transistor-level circuit behavior, and experience with various industry-standard tools like Cadence, HSPICE, and FineSim. Programming skills in Python/Perl for automation are valuable assets. The role demands both technical excellence and strong leadership abilities, making it perfect for someone ready to take on complex technical challenges while guiding teams and projects.
At Broadcom, you'll be part of a company that values innovation and technical excellence, working on projects that push the boundaries of semiconductor technology. The position offers the opportunity to work with cutting-edge process technologies and contribute to the development of next-generation memory solutions.
Responsibilities For Staff Engineer - Memory Design Validation
- Lead Memory Design Validation of SRAM, Multi-Ports, Register File, TCAM, and ROM memory compilers
- Perform functional verification and resolve design discrepancies
- Conduct signal integrity analysis and propose solutions
- Perform transistor level simulations for Power Up and Lock up issues
- Execute EM/IR analysis/simulations and evaluate timing impact
- Validate timing and internal margins
- Perform QA and validation checks for timing and power models
- Develop automation scripts for verification flow
- Support silicon debugging
- Coordinate with memory design leads and managers on validation plans
Requirements For Staff Engineer - Memory Design Validation
- Strong expertise in memory macro development
- Strong understanding of transistor level circuit behavior
- Knowledge of layout challenges in sub-nanometer process technologies
- Understanding of signal integrity, EM/IR, and reliability analysis
- Knowledge of memory behavioral and physical models
- Understanding of DFT Schemes and chip level integration
- Proficiency in transistor level simulators
- Experience with Cadence schematic/layout editor tools
- Experience with HSPICE, HSIM, XA, FineSim, XARA, nWave
- Skill/Perl/Python Scripting experience
- Good communication and leadership skills
- Strong debugging and problem-solving skills
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