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ASIC Design Verification Engineer

Global technology company that designs, manufactures, and sells networking hardware, software, and telecommunications equipment.
Embedded
Mid-Level Software Engineer
In-Person
5,000+ Employees
3+ years of experience
Enterprise SaaS

Description For ASIC Design Verification Engineer

Cisco's Common ASIC Group is seeking a talented Verification Engineer to drive existing projects and engage in new development of next-generation switching systems. This role involves working with Cisco's best-in-class switching solution team, focusing on developing ASICs at the heart of switch products. The position offers an opportunity to work on cutting-edge technology that powers internet infrastructure worldwide.

As an ASIC Design Verification Engineer, you'll be responsible for developing and enhancing test benches, implementing verification methodologies, and ensuring the quality of complex ASIC designs. You'll collaborate closely with design and hardware teams across various stages - from simulation to emulation and ASIC bring-up.

Cisco offers a collaborative environment where innovation is encouraged, and diversity is celebrated. The company provides comprehensive benefits including medical, dental, and vision insurance, 401(k) with matching, flexible vacation policies, and opportunities for professional growth. This role combines technical challenges with the opportunity to impact global internet infrastructure.

The ideal candidate will bring strong experience in System Verilog and UVM methodology, complemented by knowledge of C++ and scripting languages. You'll be part of a team that values both technical excellence and collaborative spirit, working on projects that directly influence how data moves across the internet.

Last updated 2 months ago

Responsibilities For ASIC Design Verification Engineer

  • Designing UVM/SystemVerilog testbenches
  • Defining new DV methodologies
  • Enhancing existing testbenches
  • End-to-end verification of various design blocks
  • Contributing to top level verification
  • Be a part of emulation testing efforts
  • Participate in the ASIC bring-up

Requirements For ASIC Design Verification Engineer

Python
  • Bachelor's or master's degree in EE and CE
  • 3+ years of ASIC Design Verification
  • Hands-on experience on System Verilog and UVM methodology
  • Ability to construct testbench including scoreboard, agents, sequencers, and monitors
  • Ability to debug issues independently
  • Proficient in constrained random DV environments
  • Good written and verbal communication skills

Benefits For ASIC Design Verification Engineer

401k
Medical Insurance
Dental Insurance
Vision Insurance
  • Medical insurance
  • Dental insurance
  • Vision insurance
  • 401(k) plan with company matching
  • Short and long-term disability coverage
  • Basic life insurance
  • Paid holidays
  • Vacation Time Off
  • Sick Time Off
  • Volunteer time off

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