ASIC DFT Engineering Technical Leader :: Design for testability, JTAG, Scan and BIST :: Exp 8+ years

Join Cisco's Common Hardware Group (CHG), a dynamic team responsible for delivering silicon, optics, and hardware platforms for Cisco's core Switching, Routing, and Wireless products. As an ASIC DFT Engineering Technical Leader, you'll be at the forefront of implementing Hardware Design-for-Test features that support ATE, in-system test, debug, and diagnostics needs. The role involves developing innovative DFT IP, collaborating with cross-functional teams, and integrating test logic throughout the implementation process.

Working with Cisco Silicon One, you'll contribute to the only unifying silicon architecture in the market that enables customers to deploy best-of-breed silicon across various applications. The position requires expertise in Jtag protocols, Scan and BIST architectures, and proficiency with industry-standard ATPG and EDA tools.

At Cisco, you'll be part of a culture that embraces digital transformation and innovation. The company values diversity, creativity, and even celebrates failure as a learning opportunity. With over 36 years of experience, Cisco continues to evolve beyond hardware, encompassing software and security solutions while maintaining its position as an industry leader in networking technology.

The role offers comprehensive benefits including medical, dental, and vision insurance, 401k with company match, disability coverage, and flexible time off policies. You'll also have opportunities for professional growth, collaboration with talented teams, and the chance to make a significant impact on next-generation silicon solutions.