STA Engineer

eInfochips, a subsidiary of Arrow Electronics (Fortune #133), is seeking a Senior STA (Static Timing Analysis) Engineer to join their team in San Jose, CA. This role combines deep technical expertise in ASIC design with leadership responsibilities, requiring 7+ years of experience for candidates with a Bachelor's degree or 5+ years for those with a Master's in Electrical or Computer Engineering.

The position involves working with cutting-edge timing analysis tools and methodologies, focusing on fullchip SDC development and timing closure across multiple modes. The successful candidate will play a crucial role in developing and implementing efficient methodologies for block-to-fullchip SDC promotion and ensuring timing quality throughout the design cycle.

Key responsibilities include overseeing fullchip SDCs, collaborating with physical design and DFT teams, and mentoring other RTL design owners. The role offers opportunities to work with advanced tools like PrimeTime/Tempus, synthesis tools, and formal verification tools, while also requiring expertise in scripting languages such as Python, Perl, or TCL.

The company offers a comprehensive benefits package including medical, dental, and vision insurance, 401k with matching contributions, disability insurance, HSA/HRA options, paid time off, and tuition reimbursement. As part of Arrow Electronics, eInfochips has a strong global presence with over 500+ products developed and 40M deployments across 140 countries, providing excellent opportunities for professional growth and development in the semiconductor industry.

This is an in-person position at the San Jose office, offering the chance to work directly with cross-functional teams and contribute to complex ASIC designs. The role combines technical depth with leadership opportunities, making it ideal for experienced engineers looking to advance their careers in semiconductor design.