ASIC Design Engineer, Silicon
Description For ASIC Design Engineer, Silicon
Google is seeking an experienced ASIC Design Engineer to join their Silicon team, focusing on developing custom silicon solutions for Google's direct-to-consumer products. This role is integral to the team that pushes boundaries in hardware innovation, contributing to products used by millions worldwide. The position involves designing foundation and chassis IPs, including Network on Chip (NoC), Clock, Debug, IPC, Memory Management Unit (MMU), and other peripherals for Pixel System on Chip (SoCs).
The ideal candidate will collaborate across multiple teams, including architecture, software, verification, power, and timing synthesis, to deliver high-quality Register-Transfer Level (RTL) designs. They will be responsible for solving technical problems related to micro-architecture and low power design methodology, while evaluating design options with a focus on performance, power, and area optimization.
This role combines hardware engineering expertise with software development, requiring proficiency in both RTL design using Verilog/SystemVerilog and programming languages like Python or Perl. The position offers the opportunity to work on cutting-edge technology that shapes the future of Google's hardware experiences, delivering unparalleled performance, efficiency, and integration.
Working at Google's Bengaluru office, you'll be part of a global team that combines the best of Google AI, Software, and Hardware to create radically helpful experiences. The role requires strong technical skills, collaborative abilities, and a passion for pushing the boundaries of what's possible in custom silicon design.
Responsibilities For ASIC Design Engineer, Silicon
- Participate in test planning and coverage analysis
- Develop Register-Transfer Level (RTL) implementations that meet power, performance and area goals
- Participate in synthesis, timing/power closure and Field Programmable Gate Array (FPGA) and silicon bring-up
- Perform Verilog/SystemVerilog RTL coding, functional, performance simulation debug and Lint/CDC/FV/UPF checks
- Create tools/scripts to automate tasks and track progress
Requirements For ASIC Design Engineer, Silicon
- Bachelor's degree in Electrical or Computer Engineering or equivalent practical experience
- 6 years of experience with ARM-based System on a chip (SoCs), interconnects and Application-Specific Integrated Circuit (ASIC) methodology
- 5 years of experience with Register-Transfer Level (RTL) design using Verilog/System Verilog and microarchitecture
- Experience with a coding language like Python or Perl
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