ASIC Design for Testability Engineer, Silicon
Description For ASIC Design for Testability Engineer, Silicon
Google is seeking an ASIC Design for Testability Engineer to join their Silicon team, working on custom silicon solutions that power Google's direct-to-consumer products. This role is part of Google's mission to organize the world's information and make it universally accessible through innovative hardware experiences.
The position requires expertise in Design for Testability (DFT) and Design for Debug (DFD) methodologies, with a focus on developing and implementing test architectures for complex silicon designs. The successful candidate will work with cutting-edge technology, defining specifications and developing flows for new technology node implementations.
Key responsibilities include implementing and verifying DFT logic components such as memory built-in self test (MBIST), scan chains, and TAP controllers. The role involves close collaboration with silicon engineering teams for test planning and pattern generation, as well as participating in critical post-silicon activities including bring-up, diagnostics, and characterization.
The ideal candidate will have at least 4 years of experience in DFT/DFD flows, with expertise in various test standards and formats. Experience with industry-standard EDA tools and familiarity with User Defined Fault Models (UDFM) is highly valued. The role offers the opportunity to work with state-of-the-art tools and methodologies while contributing to products used by millions worldwide.
This position at Google offers the chance to be part of a team that pushes boundaries in hardware development, working on projects that directly impact the future of Google's consumer products. The role combines technical expertise with collaborative teamwork, offering opportunities for professional growth while contributing to innovative solutions in silicon design and testing.
Responsibilities For ASIC Design for Testability Engineer, Silicon
- Define DFX specifications and develop flows and methodologies for new technology node implementation
- Implement/Integrate and verify DFT logic
- Work with the silicon engineering team to create test plans and generate test patterns
- Participate in post-silicon activity like bring up, diagnostics, and characterization
- Work with EDA and IP vendors to incorporate state-of-the-art DFT/DFD/DFY flows and methodologies
Requirements For ASIC Design for Testability Engineer, Silicon
- Bachelor's degree or equivalent practical experience
- 4 years of experience in DFT/DFD flows and methodologies
- Experience developing DFT specifications and driving DFT architecture
- Experience with User Defined Fault Models (UDFM) generation
- Experience with STA constraints development and analysis
- Experience using EDA tools like Design Compiler, DFT Max, FastScan, TetraMax
- Experience in silicon bring-up, debug, and validation of DFT features
Benefits For ASIC Design for Testability Engineer, Silicon
- Equal Employment Opportunity
- Accommodation for special needs
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