ASIC Design for Testability Engineer, Silicon
Description For ASIC Design for Testability Engineer, Silicon
Google is seeking an ASIC Design for Testability Engineer to join their Silicon team in Bengaluru. This role is part of Google's hardware innovation team that develops custom silicon solutions powering their direct-to-consumer products. The position combines hardware expertise with Google's cutting-edge AI and software capabilities to create next-generation computing experiences.
The ideal candidate will have deep expertise in DFT/DFD methodologies and silicon validation. You'll be responsible for defining specifications, implementing test logic, and working closely with silicon engineering teams to ensure robust testing solutions. The role requires hands-on experience with industry-standard EDA tools and test standards.
As part of Google's hardware team, you'll contribute to products used by millions worldwide, focusing on performance, efficiency, and integration. The position offers the opportunity to work on cutting-edge silicon development while collaborating with world-class engineers and researchers.
Google offers a collaborative environment with excellent benefits and the chance to impact products at global scale. The role requires strong technical skills combined with the ability to work cross-functionally with various engineering teams. If you're passionate about hardware innovation and want to shape the future of Google's silicon technology, this position offers an exciting opportunity to make a significant impact.
Responsibilities For ASIC Design for Testability Engineer, Silicon
- Define DFX specifications and develop flows and methodologies for new technology node implementation
- Implement/Integrate and verify DFT logic
- Work with the silicon engineering team to create test plans and generate test patterns
- Participate in post-silicon activity like bring up, diagnostics, and characterization
- Work with EDA and IP vendors to incorporate state-of-the-art DFT/DFD/DFY flows
Requirements For ASIC Design for Testability Engineer, Silicon
- Bachelor's degree or equivalent practical experience
- 4 years of experience in DFT/DFD flows and methodologies
- Experience developing DFT specifications and driving DFT architecture
- Experience with User Defined Fault Models (UDFM) generation
- Experience with STA constraints development and analysis
- Experience using EDA tools like Design Compiler, DFT Max, FastScan, TetraMax
- Experience in silicon bring-up, debug, and validation
- Knowledge of various test standards
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