ASIC Design Verification Engineer, Machine Learning
Description For ASIC Design Verification Engineer, Machine Learning
In this role, you'll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You'll be part of a diverse team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.
Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.
As an ASIC Design Verification Engineer specializing in Machine Learning at Google, you will:
- Work on cutting-edge TPU (Tensor Processing Unit) technology
- Develop custom silicon solutions for AI/ML applications
- Verify complex digital designs, focusing on TPU architecture
- Collaborate with a diverse team to push boundaries in hardware acceleration
- Contribute to products used by millions worldwide
- Be part of the Technical Infrastructure team, ensuring smooth operations of Google's platforms
This role offers an exciting opportunity to shape the future of AI/ML hardware and make a significant impact on Google's technology infrastructure.
Responsibilities For ASIC Design Verification Engineer, Machine Learning
- Plan the verification of digital design blocks by understanding the design specification and interacting with design engineers to identify important verification scenarios.
- Create and enhance constrained-random verification environments using SystemVerilog and Universal Verification Methodology (UVM), or verify designs with SVA and industry leading formal tools.
- Identify and write all types of coverage measures for stimulus and corner-cases.
- Debug tests with design engineers to deliver functionally correct design blocks.
- Close coverage measures to identify verification holes and to show progress towards tape-out.
Requirements For ASIC Design Verification Engineer, Machine Learning
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
- 2 years of experience with industry-standard tools, languages and methodologies relevant to the development of silicon-based ICs and chips.
- Experience with SystemVerilog (e.g.,SystemVerilog Assertions or functional coverage).
Benefits For ASIC Design Verification Engineer, Machine Learning
- Equity
