ASIC DFT Engineer
Description For ASIC DFT Engineer
Google is seeking an ASIC DFT (Design for Testing) Engineer to join their Devices & Services team, which combines Google's AI, Software, and Hardware expertise to create innovative user experiences. This role is part of a team that develops custom silicon solutions powering Google's direct-to-consumer products.
The position requires expertise in DFT methodologies and tools, working closely with RTL and physical designer engineers to implement testing solutions for complex System on Chip (SoC) designs. You'll be responsible for subsystem level DFT scan insertion, ATPG, and Gate Level Simulation, ensuring the testability and quality of Google's hardware products.
This is an excellent opportunity for someone with a background in Electrical or Electronics Engineering who has experience with DFT tools like Tessent and various testing methodologies including ATPG, BIST, and JTAG. The role combines hands-on technical work with collaborative team efforts, contributing to Google's mission of organizing world's information and making it universally accessible.
The position offers the chance to work on cutting-edge hardware development at one of the world's leading technology companies. You'll be part of a team that pushes boundaries in silicon development, directly impacting products used by millions of people worldwide. The role requires both technical expertise and the ability to work effectively with various engineering teams to deliver comprehensive testing solutions for complex semiconductor designs.
Responsibilities For ASIC DFT Engineer
- Work with a team of Design for Testing (DFT) engineers, Register-Transfer Level (RTL) and physical designer engineers
- Work on subsystem level DFT scan insertion, ATPG, no timing and timing Gate Level Simulation (GLS)
- Work with executive members of the DFT team to deliver overall deliverables for subsystems in a System on a Chip (SoC)
Requirements For ASIC DFT Engineer
- Bachelor's degree in Electrical or Electronics Engineering, or equivalent practical experience
- 2 years of experience in DFT methodologies
- Experience with DFT Electronic Design Automation (EDA) tools like Tessent
- Experience with Automatic Test Pattern Generation (ATPG), Low Power designs, Built-In Self Test (BIST), Joint Test Action Group (JTAG), Internal Joint Test Action Group (IJTAG) tools and flow
- Experience working with DFT scan insertion, ATPG and Gate level simulations
- Experience with a scripting language such as Perl or Python
- Knowledge on IJTAG, Streaming Scan Network (SSN)
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