ASIC DFT Engineer, Silicon
Description For ASIC DFT Engineer, Silicon
Join Google's Devices & Services team as an ASIC DFT Engineer, where you'll be part of a team pushing boundaries in custom silicon solutions that power Google's direct-to-consumer products. This role combines the best of Google AI, Software, and Hardware to create innovative experiences for users worldwide.
As a DFT Engineer, you'll work closely with RTL and Physical Designer Engineers, focusing on developing and implementing Design for Testing methodologies. You'll be responsible for subsystem level DFT scan and Memory Built-In Self Test architecture, handling multiple voltage and power domains. The role requires expertise in DFT Electronic Design Automation tools and various testing methodologies including ATPG, BIST, and JTAG.
The position offers the opportunity to contribute to Google's hardware innovation, working on products used by millions globally. You'll be part of Google's mission to organize world's information and make it universally accessible, specifically through hardware advancement. The team researches, designs, and develops new technologies to make computing interactions faster, seamless, and more powerful.
This is an excellent opportunity for someone with strong technical skills in hardware design and testing, combined with scripting abilities in Python and TCL. You'll be working in Bengaluru, India, collaborating with various engineering teams to ensure the quality and testability of Google's silicon products. The role offers the chance to work on cutting-edge technology while being part of Google's inclusive and innovative culture.
Responsibilities For ASIC DFT Engineer, Silicon
- Work on Subsystem level DFT scan, Memory Built-In Self Test (MBIST) architecture with multiple voltage, power domains
- Write basic scripts to automate the DFT flow
- Develop tests that can be used for production in the Automatic Test Equipment (ATE) flow
Requirements For ASIC DFT Engineer, Silicon
- Bachelor's degree in Electrical or Electronics Engineering, or equivalent practical experience
- 3 years of experience in DFT methodologies
- Experience with DFT Electronic Design Automation (EDA) tools like Tessent
- Experience with Automatic Test Pattern Generation (ATPG), Low Power designs, Built-In Self Test (BIST), Joint Test Action Group (JTAG), Internal Joint Test Action Group (IJTAG) tools and flow
- Experience architecting/developing DFT flows and methodologies
- Experience in collaborating with Design, Physical Design (PD) and Static Timing Analysis (STA) teams
- Excellent scripting skills in languages like Python and TCL
Benefits For ASIC DFT Engineer, Silicon
- Equal employment opportunity
- Accommodations for special needs
- Global collaboration opportunities
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