ASIC DFT Engineer, Silicon
Description For ASIC DFT Engineer, Silicon
Join Google's Devices & Services team as an ASIC DFT Engineer, where you'll be at the forefront of developing custom silicon solutions that power Google's direct-to-consumer products. This role combines the best of Google AI, Software, and Hardware to create innovative experiences for users worldwide. As part of the DFT Engineering team, you'll work closely with RTL and Physical Designer Engineers to implement testing methodologies for complex silicon designs.
The position requires expertise in DFT methodologies, including scan architecture, MBIST, and various testing protocols like JTAG and IJTAG. You'll be responsible for developing and automating DFT flows, working with multiple voltage and power domains, and creating production-ready tests for ATE flow. The role demands strong technical skills in EDA tools like Tessent and proficiency in scripting languages such as Python and TCL.
This opportunity is ideal for someone who wants to contribute to groundbreaking hardware development at one of the world's leading technology companies. You'll be part of a team that pushes boundaries in silicon design, working on products that millions of users rely on daily. The role offers the chance to work with cutting-edge technology while collaborating with various engineering teams to ensure the highest quality and testability of Google's custom silicon solutions.
Google's commitment to innovation in hardware, combined with its mission to organize the world's information and make it universally accessible, makes this an exciting opportunity for engineers passionate about advancing hardware technology. The role is based in Bengaluru, India, where you'll be part of a dynamic team working on next-generation hardware experiences.
Responsibilities For ASIC DFT Engineer, Silicon
- Work on Subsystem level DFT scan, Memory Built-In Self Test (MBIST) architecture with multiple voltage, power domains
- Write basic scripts to automate the DFT flow
- Develop tests that can be used for production in the Automatic Test Equipment (ATE) flow
Requirements For ASIC DFT Engineer, Silicon
- Bachelor's degree in Electrical or Electronics Engineering, or equivalent practical experience
- 3 years of experience in DFT methodologies
- Experience with DFT Electronic Design Automation (EDA) tools like Tessent
- Experience with Automatic Test Pattern Generation (ATPG), Low Power designs, Built-In Self Test (BIST), Joint Test Action Group (JTAG), Internal Joint Test Action Group (IJTAG) tools and flow
- Experience architecting/developing DFT flows and methodologies
- Experience in collaborating with Design, Physical Design (PD) and Static Timing Analysis (STA) teams
- Excellent scripting skills in languages like Python and TCL
Jobs Related To Google ASIC DFT Engineer, Silicon
