ASIC DFT Engineer, Silicon
Description For ASIC DFT Engineer, Silicon
Join Google's Devices & Services team as an ASIC DFT Engineer, where you'll be at the forefront of developing custom silicon solutions that power Google's direct-to-consumer products. This role combines the best of Google AI, Software, and Hardware to create groundbreaking user experiences.
As a DFT Engineer, you'll work closely with RTL and Physical Designer Engineers, focusing on critical testing methodologies and implementations. You'll be responsible for developing and implementing sophisticated testing architectures, including Memory Built-In Self Test (MBIST) with multiple voltage and power domains.
The position requires expertise in DFT methodologies, EDA tools, and various testing protocols including ATPG, BIST, and JTAG. You'll be writing automation scripts and developing production-ready tests for ATE flow, directly contributing to the quality and reliability of Google's hardware products.
Google's commitment to innovation in hardware experiences means you'll be working on projects that impact millions of users worldwide. The role offers the opportunity to shape the next generation of hardware experiences, focusing on unparalleled performance, efficiency, and integration.
This is an excellent opportunity for someone with strong technical skills in hardware testing and verification, combined with programming capabilities in Python and TCL. You'll be part of a collaborative environment, working with various engineering teams to ensure the highest quality standards in Google's hardware products.
The position is based in Bengaluru, India, offering the chance to work with Google's world-class engineering teams while contributing to products that push the boundaries of what's possible in consumer hardware.
Responsibilities For ASIC DFT Engineer, Silicon
- Work on Subsystem level DFT scan, Memory Built-In Self Test (MBIST) architecture with multiple voltage, power domains
- Write basic scripts to automate the DFT flow
- Develop tests that can be used for production in the Automatic Test Equipment (ATE) flow
Requirements For ASIC DFT Engineer, Silicon
- Bachelor's degree in Electrical or Electronics Engineering, or equivalent practical experience
- 3 years of experience in DFT methodologies
- Experience with DFT Electronic Design Automation (EDA) tools like Tessent
- Experience with Automatic Test Pattern Generation (ATPG), Low Power designs, Built-In Self Test (BIST), Joint Test Action Group (JTAG), Internal Joint Test Action Group (IJTAG) tools and flow
- Experience architecting/developing DFT flows and methodologies
- Experience in collaborating with Design, Physical Design (PD) and Static Timing Analysis (STA) teams
- Excellent scripting skills in languages like Python and TCL
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