ASIC DFT Engineer, Silicon
Description For ASIC DFT Engineer, Silicon
Join Google's Devices & Services team as an ASIC DFT Engineer, where you'll be at the forefront of developing custom silicon solutions that power Google's direct-to-consumer products. This role combines the best of Google AI, Software, and Hardware to create innovative experiences for users worldwide. You'll work within a team of Design for Testing (DFT) Engineers, collaborating closely with RTL and Physical Designer Engineers to push the boundaries of hardware development.
The position involves working on complex subsystem level DFT scan and Memory Built-In Self Test architecture, handling multiple voltage and power domains. You'll be responsible for automating DFT flows through scripting and developing production-ready tests for Automatic Test Equipment flow. This role requires expertise in DFT methodologies, EDA tools, and various testing protocols including ATPG, BIST, and JTAG.
As part of Google's mission to organize the world's information and make it universally accessible, you'll contribute to research, design, and development of new technologies that make computing faster and more seamless. The role offers the opportunity to work on cutting-edge hardware projects that directly impact millions of users, focusing on improving interaction methods and advancing form factors.
The ideal candidate will bring a strong background in electrical or electronics engineering, proven experience with DFT methodologies, and excellent scripting skills. You'll be part of a team that values innovation, collaboration, and technical excellence, working in an environment that pushes the boundaries of what's possible in hardware development.
Responsibilities For ASIC DFT Engineer, Silicon
- Work on Subsystem level DFT scan, Memory Built-In Self Test (MBIST) architecture with multiple voltage, power domains
- Write basic scripts to automate the DFT flow
- Develop tests that can be used for production in the Automatic Test Equipment (ATE) flow
Requirements For ASIC DFT Engineer, Silicon
- Bachelor's degree in Electrical or Electronics Engineering, or equivalent practical experience
- 3 years of experience in DFT methodologies
- Experience with DFT Electronic Design Automation (EDA) tools like Tessent
- Experience with Automatic Test Pattern Generation (ATPG), Low Power designs, Built-In Self Test (BIST), Joint Test Action Group (JTAG), Internal Joint Test Action Group (IJTAG) tools and flow
- Experience architecting/developing DFT flows and methodologies
- Experience in collaborating with Design, Physical Design (PD) and Static Timing Analysis (STA) teams
- Excellent scripting skills in languages like Python and TCL
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