ASIC Engineer, Network on Chip, Intellectual Property Design
Description For ASIC Engineer, Network on Chip, Intellectual Property Design
Google is seeking an experienced ASIC Engineer to join their team working on Network on Chip and Intellectual Property Design. This role is part of Google's hardware innovation team that develops custom silicon solutions powering their direct-to-consumer products. The position focuses on designing foundation and chassis IPs for Pixel System on Chip (SoCs), including Network on Chip (NoC), Clock, Debug, IPC, Memory Management Unit (MMU) and other peripherals.
The ideal candidate will collaborate across multiple teams including architecture, software, verification, power, and timing to deliver high-quality Register-Transfer Level (RTL) designs. They will be responsible for solving technical problems related to micro-architecture and low power design methodology, while evaluating design options with consideration for performance, power, and area optimization.
This role offers the opportunity to work on cutting-edge hardware technology that impacts millions of users worldwide. The position requires deep expertise in ASIC design, RTL development, and system architecture, combining technical skills with collaborative teamwork to drive innovation in Google's hardware products.
The role is based in Bengaluru, India, and requires significant experience in ARM-based SoCs, interconnects, and ASIC methodology. The successful candidate will contribute to Google's mission of organizing the world's information while working on advanced hardware solutions that push the boundaries of technology.
Google offers a collaborative work environment and the chance to work on products that make a real difference in people's lives. The role provides opportunities for professional growth and the satisfaction of seeing your work implemented in widely-used consumer products.
Responsibilities For ASIC Engineer, Network on Chip, Intellectual Property Design
- Work as part of the team that delivers coherent fabric interconnect solutions
- Define microarchitecture details such as interface protocol, block diagram, data flow, pipelines, etc
- Perform RTL development (SystemVerilog), debug functional/performance simulations
- Perform RTL quality checks including Lint, CDC, Synthesis, Unified Power Format (UPF) checks
- Participate in synthesis, timing/power estimation and field-programmable gate array (FPGA)/silicon bring-up
Requirements For ASIC Engineer, Network on Chip, Intellectual Property Design
- Bachelor's degree in Electrical or Computer Engineering or equivalent practical experience
- 6 years of experience with ARM-based System on a chip (SoCs), interconnects and Application-Specific Integrated Circuit (ASIC) methodology
- 5 years of experience with Register-Transfer Level (RTL) design using Verilog/System Verilog and microarchitecture
- Experience with a coding language like Python or Perl
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