ASIC Engineer, Network on Chip, Intellectual Property Design
Description For ASIC Engineer, Network on Chip, Intellectual Property Design
Google is seeking an experienced ASIC Engineer to join their team working on Network on Chip and Intellectual Property Design. This role is part of Google's hardware division that develops custom silicon solutions powering their direct-to-consumer products. The position focuses on designing foundation and chassis IPs for Pixel System on Chip (SoCs), including Network on Chip (NoC), Clock, Debug, IPC, and Memory Management Unit (MMU).
The ideal candidate will have extensive experience in ARM-based SoCs, ASIC methodology, and RTL design using Verilog/System Verilog. They will work collaboratively with various teams including architecture, software, verification, power, and timing to deliver high-quality RTL designs. The role requires strong technical problem-solving skills in micro-architecture and low power design methodology, with a focus on optimizing performance, power, and area.
This is an opportunity to contribute to Google's mission of organizing world's information and making it universally accessible through hardware innovation. The team combines Google's expertise in AI, Software, and Hardware to create groundbreaking user experiences. The position offers the chance to work on technologies that will shape the next generation of Google's hardware products, impacting millions of users worldwide.
The role requires a strong foundation in electrical or computer engineering, with hands-on experience in IP design, RTL quality checks, and various methodologies for power estimation and timing closure. The successful candidate will be part of Google's innovative hardware team, working on cutting-edge technology while collaborating with world-class engineers and researchers.
Responsibilities For ASIC Engineer, Network on Chip, Intellectual Property Design
- Work as part of the team that delivers coherent fabric interconnect solutions
- Define microarchitecture details such as interface protocol, block diagram, data flow, pipelines, etc
- Perform RTL development (SystemVerilog), debug functional/performance simulations
- Perform RTL quality checks including Lint, CDC, Synthesis, Unified Power Format (UPF) checks
- Participate in synthesis, timing/power estimation and field-programmable gate array (FPGA)/silicon bring-up
Requirements For ASIC Engineer, Network on Chip, Intellectual Property Design
- Bachelor's degree in Electrical or Computer Engineering or equivalent practical experience
- 6 years of experience with ARM-based System on a chip (SoCs), interconnects and Application-Specific Integrated Circuit (ASIC) methodology
- 5 years of experience with Register-Transfer Level (RTL) design using Verilog/System Verilog and microarchitecture
- Experience with a coding language like Python or Perl
Jobs Related To Google ASIC Engineer, Network on Chip, Intellectual Property Design
