ASIC Engineer, Network on Chip, Intellectual Property Design
Description For ASIC Engineer, Network on Chip, Intellectual Property Design
Google is seeking an experienced ASIC Engineer to join their team working on Network on Chip and Intellectual Property Design. This role is part of Google's hardware innovation team that develops custom silicon solutions powering their direct-to-consumer products. The position focuses on designing foundation and chassis IPs for Pixel System on Chips (SoCs), including Network on Chip (NoC), Clock, Debug, IPC, and Memory Management Unit (MMU).
The ideal candidate will have extensive experience in ARM-based SoCs, RTL design, and ASIC methodology. They will work collaboratively with various teams including architecture, software, verification, power, and timing to deliver high-quality RTL designs. The role requires strong technical problem-solving skills in micro-architecture and low power design methodology, with a focus on optimizing performance, power, and area.
This is an opportunity to directly impact Google's hardware experiences, working on products used by millions worldwide. The position combines cutting-edge hardware design with Google's expertise in AI and software, aiming to create radically helpful experiences for users. The role offers the chance to work with state-of-the-art technology while contributing to Google's mission of organizing the world's information and making it universally accessible.
The position is based in Bengaluru, India, and requires collaboration with global teams. Successful candidates will need to balance technical expertise with strong communication skills, as they'll be working across different departments to bring innovative hardware solutions to life. This role represents a unique opportunity to shape the future of Google's hardware products while working with some of the most advanced silicon technology in the industry.
Responsibilities For ASIC Engineer, Network on Chip, Intellectual Property Design
- Work as part of the team that delivers coherent fabric interconnect solutions
- Define microarchitecture details such as interface protocol, block diagram, data flow, pipelines, etc.
- Perform RTL development (SystemVerilog), debug functional/performance simulations
- Perform RTL quality checks including Lint, CDC, Synthesis, Unified Power Format (UPF) checks
- Participate in synthesis, timing/power estimation and field-programmable gate array (FPGA)/silicon bring-up
Requirements For ASIC Engineer, Network on Chip, Intellectual Property Design
- Bachelor's degree in Electrical or Computer Engineering or equivalent practical experience
- 6 years of experience with ARM-based System on a chip (SoCs), interconnects and Application-Specific Integrated Circuit (ASIC) methodology
- 5 years of experience with Register-Transfer Level (RTL) design using Verilog/System Verilog and microarchitecture
- Experience with a coding language like Python or Perl
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