ASIC Physical Design Engineer

Google is seeking an ASIC Physical Design Engineer to join their Chip Implementation team, focusing on the physical implementation of ASICs in advanced technology nodes. This role is part of the ML, Systems, & Cloud AI (MSCA) organization, which is responsible for the hardware, software, and infrastructure powering Google's services and Cloud platform.

The position offers an exciting opportunity to shape the future of AI/ML hardware acceleration through work on Google's TPU (Tensor Processing Unit) technology. You'll be at the forefront of developing custom silicon solutions that power Google's most demanding AI/ML applications, working with cutting-edge technology that impacts products used by millions worldwide.

Key responsibilities include physical design work encompassing place and route, EMIR, static timing, and physical verification. The role requires going beyond automated flow execution to provide customized solutions using industry-standard EDA CAD tools, optimizing Power Performance Area (PPA).

The ideal candidate should have a strong background in electrical engineering or computer science, with specific expertise in physical design and methodologies. Experience with physical IP integration, silicon interposer design, and advanced process nodes is highly valued. The role offers competitive compensation including base salary, bonus, equity, and comprehensive benefits.

This position is based in Sunnyvale, CA, and is part of Google's larger mission to advance computing technology while prioritizing security, efficiency, and reliability. You'll be contributing to projects that have global impact, from developing TPUs to supporting Google Cloud's Vertex AI platform for enterprise customers.

Join a team that's pushing the boundaries of what's possible in AI/ML hardware acceleration and be part of shaping the future of hyperscale computing at one of the world's leading technology companies.