ASIC Power Efficiency Engineer

Google is seeking an ASIC Power Efficiency Engineer to join their TPU Power Design team, working on cutting-edge custom silicon solutions that power Google's direct-to-consumer products. This role is part of the ML, Systems, & Cloud AI (MSCA) organization, which is responsible for the hardware, software, and infrastructure that powers Google's services and Cloud platform.

The position involves working on power architecture and microarchitecture for TPUs, spanning pre-silicon power modeling to post-silicon data collection and analysis. The successful candidate will drive design power analysis and help define improvements to achieve more power-efficient designs. This role requires a solid understanding of power fundamentals and silicon design concepts, along with experience in performing chip power rollups.

Key responsibilities include driving power analysis for silicon designs, developing tests and benchmarks for measuring chip power consumption, and collaborating with cross-functional teams to define power strategy and specifications. The role offers the opportunity to work on innovative hardware experiences that deliver unparalleled performance and efficiency.

The ideal candidate will have at least 3 years of experience in ASIC design, proficiency in scripting languages like Python, and experience with chip power analysis. Preferred qualifications include advanced degrees in relevant fields, experience with EDA tools such as PTPX or PowerArtist, and expertise in RTL languages like SystemVerilog.

This position offers competitive compensation including a base salary range of $132,000-$189,000, plus bonus, equity, and comprehensive benefits. The role is based in Sunnyvale, CA, and is part of Google's commitment to pushing boundaries in hardware development and innovation. Join a team that directly impacts the future of Google's hardware experiences and serves billions of users worldwide.