ASIC Power Management Architect, Silicon
Description For ASIC Power Management Architect, Silicon
Join Google's innovative hardware team as an ASIC Power Management Architect, where you'll be at the forefront of developing custom silicon solutions that power Google's direct-to-consumer products. This role combines advanced power management architecture with cutting-edge hardware development, focusing on maximizing performance under power and thermal constraints.
As part of Google's mission to organize the world's information, you'll work with a team that combines the best of Google AI, Software, and Hardware to create radically helpful experiences. Your expertise in power management architecture will be crucial in designing and implementing solutions for next-generation SoC systems, particularly focusing on functions like image compute and CPU/GPU integration.
The role requires deep technical knowledge in power management systems, including Dynamic Voltage Frequency Scaling (DVFS) and thermal mitigation strategies. You'll be responsible for prototyping, validating, and documenting power management solutions while collaborating closely with software and power architecture teams to ensure optimal system-level designs.
This position offers the opportunity to directly impact millions of users worldwide through Google's hardware products, working at the intersection of power efficiency and performance optimization. The ideal candidate will bring both technical expertise and collaborative skills to help drive innovation in hardware experiences.
Your work will be essential in pushing the boundaries of what's possible in hardware performance and efficiency, contributing to Google's broader mission of making technology more helpful and accessible to users worldwide. Join a team that values innovation, technical excellence, and the ability to solve complex challenges in power management architecture.
Responsibilities For ASIC Power Management Architect, Silicon
- Define ASIC power management architecture details for an ASIC that includes functions such as image compute, CPU/GPU
- Prototype and validate for the next generation SoC power management system
- Analyze implementation and models, and test the performance of power management solutions
- Produce detailed documentation for power management schemes implementation
- Collaborate with software and power architecture team to build system level designs and methods
Requirements For ASIC Power Management Architect, Silicon
- Bachelor's degree in Electrical Engineering or equivalent practical experience
- 5 years of experience in power management or post-silicon measurements and validation
- 3 years of experience with power management validation
- Knowledge of Dynamic Voltage Frequency Scaling (DVFS), idle power management, and system mitigation
- Knowledge of the impact of software and architectural design decisions on power and thermal behavior
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