ASIC Power Management Architect, Silicon
Description For ASIC Power Management Architect, Silicon
Join Google's Silicon team in developing custom silicon solutions that power the future of Google's direct-to-consumer products. As an ASIC Power Management Architect, you'll be instrumental in shaping the next generation of hardware experiences, focusing on delivering unparalleled performance and efficiency. The role combines advanced power management architecture with practical implementation, requiring expertise in DVFS, thermal management, and system-level optimization.
You'll work at the intersection of hardware and software, defining power management architectures for complex ASICs incorporating image compute and CPU/GPU functions. The position demands both technical depth in power management and the ability to collaborate across teams to create comprehensive system-level solutions.
This is an opportunity to impact Google's hardware products used by millions worldwide. You'll be part of a team that combines Google's strengths in AI, Software, and Hardware to create innovative solutions. The role requires a strong background in power management validation, system architecture, and the ability to produce detailed technical documentation and analysis.
Working at Google's Bengaluru office, you'll have access to world-class resources and collaborate with experts across different domains. The company offers a culture of innovation and the chance to work on cutting-edge technology that pushes the boundaries of what's possible in hardware design.
If you're passionate about power optimization, system architecture, and want to contribute to products that make a real difference in people's lives, this role offers the perfect blend of technical challenge and meaningful impact. Join a team that's dedicated to creating the next generation of efficient, powerful hardware solutions at one of the world's leading technology companies.
Responsibilities For ASIC Power Management Architect, Silicon
- Define ASIC power management architecture details for an ASIC that includes functions such as image compute, CPU/GPU
- Prototype and validate for the next generation SoC power management system
- Analyze implementation and models, and test the performance of power management solutions
- Produce detailed documentation for power management schemes implementation
- Collaborate with software and power architecture team to build system level designs and methods
Requirements For ASIC Power Management Architect, Silicon
- Bachelor's degree in Electrical Engineering or equivalent practical experience
- 5 years of experience in power management or post-silicon measurements and validation
- 3 years of experience with power management validation
- Knowledge of Dynamic Voltage Frequency Scaling (DVFS), idle power management, and system mitigation
- Knowledge of the impact of software and architectural design decisions on power and thermal behavior
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