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ASIC RTL Design Engineer

Google organizes the world's information and makes it universally accessible and useful, combining AI, Software, and Hardware to create helpful experiences.
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Entry-Level Software Engineer
In-Person
5,000+ Employees
3+ years of experience
Enterprise SaaS

Description For ASIC RTL Design Engineer

Join Google's innovative hardware team as an ASIC RTL Design Engineer, where you'll be at the forefront of developing custom silicon solutions that power Google's direct-to-consumer products. This role combines the best of Google's AI, Software, and Hardware capabilities to create groundbreaking technological experiences.

As an ASIC RTL Design Engineer, you'll be responsible for RTL development using SystemVerilog, performing quality checks, and working on synthesis and FPGA/silicon bring-up. You'll collaborate with multi-disciplined teams across different locations to push the boundaries of hardware innovation.

The ideal candidate should have a strong foundation in Electrical/Computer Engineering, with hands-on experience in RTL design, scripting languages, and ARM-based SoCs. Additional expertise in IP design for clocking, interconnects, and peripherals, as well as experience with low power estimation and timing closure methodologies, would be highly valuable.

This position offers the opportunity to work on products used by millions worldwide, contributing to Google's mission of organizing the world's information and making it universally accessible. You'll be part of a team that values innovation, collaboration, and technical excellence, while working in an environment that promotes equal opportunity and inclusion.

Last updated 3 days ago

Responsibilities For ASIC RTL Design Engineer

  • Perform RTL development (SystemVerilog), debug functional/performance simulations
  • Perform RTL quality checks including Lint, CDC, Synthesis, UPF checks
  • Participate in synthesis, timing/power estimation and FPGA/silicon bring-up
  • Communicate and work with multi-disciplined and multi-site teams

Requirements For ASIC RTL Design Engineer

Python
  • Bachelor's degree in Electrical/Computer Engineering
  • Experience with RTL design using Verilog/System Verilog and microarchitecture
  • Experience with a scripting language like Python or Perl
  • Experience with ARM-based SoCs, interconnects and ASIC methodology

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