ASIC RTL Design Engineer
Description For ASIC RTL Design Engineer
Join Google's hardware innovation team as an ASIC RTL Design Engineer, where you'll be at the forefront of developing custom silicon solutions that power Google's direct-to-consumer products. This role focuses on designing ASIC/SoC hardware for AI and networking accelerators that drive computational workloads across Google's product lineup, with a primary emphasis on AI acceleration. You'll be working specifically on chip-to-chip interconnect subsystems, contributing to the design, architecture, and implementation of next-generation data center accelerators.
As part of the ML, Systems, & Cloud AI (MSCA) organization, you'll be involved in shaping the future of hyperscale computing, working on projects that impact everything from Google's core services like Search and YouTube to Google Cloud offerings. The role requires expertise in RTL design using SystemVerilog, working with EDA tools, and collaborating across multiple teams including design validation, architecture, power, and physical design.
The position offers competitive compensation ranging from $132,000 to $189,000 plus bonus, equity, and comprehensive benefits. You'll be working in Sunnyvale, CA, contributing to projects that have global impact, including Google Cloud's Vertex AI platform which brings Gemini models to enterprise customers. This is an opportunity to work on cutting-edge technology while being part of a team that prioritizes security, efficiency, and reliability in everything they do.
The ideal candidate will have strong experience in ASIC design, particularly with interconnects and network subsystems, and will be comfortable working in a collaborative environment where they'll need to balance technical expertise with cross-functional teamwork. This role offers the chance to directly impact the performance and efficiency of Google's next generation of hardware experiences, making it an exciting opportunity for someone passionate about hardware design and innovation.
Responsibilities For ASIC RTL Design Engineer
- Work separately and collaboratively to create and review ASIC/SoC subsystem design architecture and microarchitecture specifications
- Develop SystemVerilog RTL to implement logic for ASIC/SoC products according to established coding and quality guidelines
- Work with design validation (DV) teams to create testplans for, verify, and debug design RTL
- Work with architecture and power teams to evaluate features and their impact
- Work with physical design teams to ensure design meets physical requirements and timing closure
Requirements For ASIC RTL Design Engineer
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience
- 3 years of experience with Register-Transfer Level (RTL) coding using Verilog/SystemVerilog
- Experience with industry-standard EDA tools for simulation, synthesis, and power analysis
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