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ASIC RTL Design Engineer

Google organizes the world's information and makes it universally accessible and useful, combining AI, Software, and Hardware to create helpful experiences.
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Entry-Level Software Engineer
In-Person
5,000+ Employees
3+ years of experience
Hardware

Description For ASIC RTL Design Engineer

Google is seeking an ASIC RTL Design Engineer to join their hardware team, focusing on developing custom silicon solutions that power Google's direct-to-consumer products. This role combines hardware engineering with Google's innovative approach to product development, working on technologies that impact millions of users worldwide.

The position requires expertise in RTL design, microarchitecture, and hardware development methodologies. You'll be working with cutting-edge technology, developing solutions that push the boundaries of hardware performance and efficiency. The role involves both technical depth in hardware design and collaboration with cross-functional teams.

As an ASIC RTL Design Engineer, you'll be responsible for the entire RTL development lifecycle, from initial design through quality checks and silicon bring-up. This includes working with SystemVerilog, performing various quality checks, and ensuring optimal timing and power performance. The role offers an opportunity to work on next-generation hardware experiences while being part of Google's mission to organize the world's information.

The ideal candidate will have a strong foundation in electrical/computer engineering, hands-on experience with RTL design, and familiarity with modern hardware development tools and methodologies. This position offers the chance to work with state-of-the-art technology while contributing to products that have a global impact.

Working at Google provides access to world-class resources and the opportunity to collaborate with industry-leading experts. The company offers a supportive environment focused on innovation and technical excellence, making it an ideal place for hardware engineers looking to make a significant impact in the field of custom silicon development.

Last updated 2 days ago

Responsibilities For ASIC RTL Design Engineer

  • Perform RTL development (SystemVerilog), debug functional/performance simulations
  • Perform RTL quality checks including Lint, CDC, Synthesis, UPF checks
  • Participate in synthesis, timing/power estimation and FPGA/silicon bring-up
  • Communicate and work with multi-disciplined and multi-site teams

Requirements For ASIC RTL Design Engineer

Python
  • Bachelor's degree in Electrical/Computer Engineering
  • Experience with RTL design using Verilog/System Verilog and microarchitecture
  • Experience with a scripting language like Python or Perl
  • Experience with ARM-based SoCs, interconnects and ASIC methodology

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