ASIC RTL Design Engineer, Machine Learning Accelerators
Description For ASIC RTL Design Engineer, Machine Learning Accelerators
Be part of a diverse team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
In this role, you will be part of a team developing cutting-edge ASICs used to accelerate Machine Learning computation in Google's data centers. You will participate in the microarchitecture, design, documentation, and implementation of the next generation of Machine Learning center accelerators.
Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.
The US base salary range for this full-time position is $127,000-$187,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. The range displayed on each job posting reflects the minimum and maximum target salaries for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training.
Responsibilities For ASIC RTL Design Engineer, Machine Learning Accelerators
- Work independently and collaboratively to create and review ASIC/SoC subsystem design architecture and microarchitecture specifications.
- Develop SystemVerilog RTL to implement logic for ASIC/SoC products according to established coding and quality guidelines.
- Work with Design Validation (DV) teams to create testplans for, verify, and debug design RTL.
- Work with physical design teams to ensure design meets physical requirements and timing closure.
Requirements For ASIC RTL Design Engineer, Machine Learning Accelerators
- Bachelor's degree in Electrical Engineering, Computer Engineering, or equivalent practical experience.
- 2 years of experience in Digital design using SystemVerilog RTL.
Benefits For ASIC RTL Design Engineer, Machine Learning Accelerators
- bonus
- equity
- benefits
