ASIC RTL Design Engineer, Silicon
Description For ASIC RTL Design Engineer, Silicon
Join Google's platform IP team designing foundation and chassis IPs for Pixel SoCs. As an ASIC RTL Design Engineer, you'll be part of a team that pushes boundaries in developing custom silicon solutions powering Google's direct-to-consumer products. You'll work on NoC, Clock, Debug, IPC, MMU and other peripherals, collaborating with architecture, software, verification, power, and timing teams to deliver quality RTL.
The role involves innovative microarchitecture development, low power design methodology, and evaluating design options for complexity, performance, and power. You'll be contributing to products used by millions worldwide, helping shape the next generation of hardware experiences with unparalleled performance, efficiency, and integration.
Google's mission focuses on organizing world's information and making it universally accessible. The team combines Google's AI, Software, and Hardware expertise to create radically helpful experiences. They research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful, aiming to improve people's lives through technology.
This position requires strong technical skills in RTL design, microarchitecture, and ASIC methodology. You'll be working with state-of-the-art technology and contributing to Google's hardware innovation. The role offers opportunities to work on cutting-edge projects while collaborating with multi-disciplined teams across different locations.
Responsibilities For ASIC RTL Design Engineer, Silicon
- Define microarchitecture details such as interface protocol, block diagram, data flow, pipelines, etc.
- Perform RTL development (SystemVerilog), debug functional/performance simulations
- Perform RTL quality checks including Lint, CDC, Synthesis, UPF checks
- Participate in synthesis, timing/power estimation, and FPGA/silicon bring-up
- Communicate and work with multi-disciplined and multi-site teams
Requirements For ASIC RTL Design Engineer, Silicon
- Bachelor's degree in Electrical/Computer Engineering or equivalent practical experience
- 2 years of experience with RTL design using Verilog/System Verilog and microarchitecture
- Experience in ARM-based SoCs, interconnects and ASIC methodology
Jobs Related To Google ASIC RTL Design Engineer, Silicon
