ASIC RTL Design Engineer, Silicon

Google is seeking an ASIC RTL Design Engineer to join their platform IP team, focusing on developing custom silicon solutions for Google's direct-to-consumer products. This role is part of a team that designs foundation and chassis IPs (NoC, Clock, Debug, IPC, MMU and other peripherals) for Pixel SoCs. The position involves collaborating with various teams including architecture, software, verification, power, and timing to deliver quality RTL designs.

The ideal candidate will contribute to innovative microarchitecture development, implement low power design methodologies, and evaluate design options considering complexity, performance, and power requirements. This role is crucial in pushing boundaries and developing solutions that power future Google hardware experiences.

As part of Google's mission to organize world's information and make it universally accessible, this position combines Google's expertise in AI, Software, and Hardware to create groundbreaking helpful experiences. The team focuses on researching, designing, and developing new technologies to make computing faster, seamless, and more powerful.

The role requires strong technical expertise in RTL design, microarchitecture development, and various methodologies for quality checks and power estimation. The successful candidate will work on projects that directly impact millions of users worldwide through Google's consumer products, while being part of a collaborative, multi-disciplined team environment.

This position offers the opportunity to work on cutting-edge technology while contributing to products that have a global impact. The role combines technical challenges with the excitement of working on next-generation hardware experiences, making it an ideal position for someone passionate about silicon design and innovation in consumer technology.