ASIC RTL Design Engineer, Silicon
Description For ASIC RTL Design Engineer, Silicon
Join Google's platform IP team designing foundation and chassis IPs for Pixel SoCs. As an ASIC RTL Design Engineer, you'll be part of a team that pushes boundaries in developing custom silicon solutions powering Google's direct-to-consumer products. You'll work on NoC, Clock, Debug, IPC, MMU and other peripherals, collaborating with architecture, software, verification, power, and timing teams to deliver quality RTL designs. The role involves innovative microarchitecture development, low power design methodology, and evaluating design options for complexity, performance, and power efficiency. You'll contribute to Google's mission of organizing world's information by creating hardware that makes computing faster and more powerful. The position requires expertise in RTL design, system architecture, and hardware development, working with cross-functional teams to develop next-generation hardware experiences. This role offers the opportunity to impact millions of users worldwide through Google's hardware products while working with cutting-edge technology and industry-leading experts.
Responsibilities For ASIC RTL Design Engineer, Silicon
- Define microarchitecture details such as interface protocol, block diagram, data flow, pipelines, etc.
- Perform RTL development (SystemVerilog), debug functional/performance simulations
- Perform RTL quality checks including Lint, CDC, Synthesis, UPF checks
- Participate in synthesis, timing/power estimation, and FPGA/silicon bring-up
- Communicate and work with multi-disciplined and multi-site teams
Requirements For ASIC RTL Design Engineer, Silicon
- Bachelor's degree in Electrical/Computer Engineering or equivalent practical experience
- 2 years of experience with RTL design using Verilog/System Verilog and microarchitecture
- Experience in ARM-based SoCs, interconnects and ASIC methodology
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