ASIC RTL Design Engineer, Silicon
Description For ASIC RTL Design Engineer, Silicon
Join Google's platform IP team designing foundation and chassis IPs for Pixel SoCs. As an ASIC RTL Design Engineer, you'll be part of a team that pushes boundaries in custom silicon solutions powering Google's direct-to-consumer products. You'll work on innovative microarchitecture and low power design methodology, collaborating with cross-functional teams in architecture, software, verification, power, and timing.
The role involves developing RTL for critical components like NoC, Clock, Debug, IPC, MMU and other peripherals. You'll be responsible for defining microarchitecture details, performing RTL development using SystemVerilog, and ensuring quality through various checks and validations. The position requires strong technical skills in ASIC design and the ability to work effectively in a multi-disciplined, multi-site environment.
Google's mission focuses on organizing world's information and making it universally accessible. This team combines Google's expertise in AI, Software, and Hardware to create groundbreaking experiences. The work directly impacts millions of users through Google's consumer products, requiring innovative solutions for performance, efficiency, and integration.
The ideal candidate will have a strong background in electrical/computer engineering, experience with RTL design and microarchitecture, and knowledge of ARM-based SoCs. Additional expertise in low power estimation, timing closure, and synthesis would be valuable. This is an opportunity to shape the future of Google's hardware experiences while working with cutting-edge technology and talented teams.
Responsibilities For ASIC RTL Design Engineer, Silicon
- Define microarchitecture details such as interface protocol, block diagram, data flow, pipelines, etc.
- Perform RTL development (SystemVerilog), debug functional/performance simulations
- Perform RTL quality checks including Lint, CDC, Synthesis, UPF checks
- Participate in synthesis, timing/power estimation, and FPGA/silicon bring-up
- Communicate and work with multi-disciplined and multi-site teams
Requirements For ASIC RTL Design Engineer, Silicon
- Bachelor's degree in Electrical/Computer Engineering or equivalent practical experience
- 2 years of experience with RTL design using Verilog/System Verilog and microarchitecture
- Experience in ARM-based SoCs, interconnects and ASIC methodology
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