Chip Package Signal and Power Integrity Engineer

$150,000 - $223,000
Embedded
Mid-Level Software Engineer
In-Person
5+ years of experience

Description For Chip Package Signal and Power Integrity Engineer

Google is seeking a Chip Package Signal and Power Integrity Engineer to join their Technical Infrastructure team. This role is crucial in developing custom silicon solutions that power Google's direct-to-consumer products. The engineer will be responsible for chip package design with signal/power integrity simulation and characterization at the chip, package, and system level.

The ideal candidate will have a strong background in Electrical Engineering or related fields, with at least 5 years of industry experience in SI/PI. They will work closely with Chip Architects, ASIC Engineers, and other SI/PI Engineers to drive chip packaging signal and power implementations from product planning to New Product Introduction (NPI).

Key responsibilities include contributing to chip-package-system co-design, developing next-generation IO interfaces, collaborating with various teams to optimize chip performance, and conducting post-silicon validation. The role requires expertise in advanced package design, including 2.5D/3D package technology, and the ability to work cross-functionally with chip design, system design, and software teams.

Google offers a competitive salary range of $150,000-$223,000, plus bonus, equity, and benefits. The company is committed to diversity and inclusion, providing equal employment opportunities to all candidates. This position offers a unique opportunity to shape the future of Google's hardware experiences, delivering unparalleled performance, efficiency, and integration in products used by millions worldwide.

Last updated 2 months ago

Responsibilities For Chip Package Signal and Power Integrity Engineer

  • Contribute to chip-package-system co-design by performing Signal Integrity (SI)/Power Integrity (PI) analysis and optimization to involve in the product definition and optimize chip floorplan, power tree structure, net lists, etc for High Performance Computing (HPC) based on 2.5D/3D package technology.
  • Develop next generation IO interfaces (serdes, memory, D2D) considering IO PHY, SI/PI and physical design.
  • Collaborate with chip design team, system design teams and suppliers to drive chip package SI/PI design target, unleash boundaries of chip performance and explore SI/PI and DFM tradeoff for advanced package design closure for production.
  • Provide feedback on chip floorplan considering IP performance/package/system routability and SI/PI.
  • Conduct post silicon validation and qualification of high speed interface for NPI.

Requirements For Chip Package Signal and Power Integrity Engineer

Python
  • Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
  • 5 years of industry experience in the SI/PI field.
  • Experience in chip package SI/PI design for interconnections and advanced package design.

Benefits For Chip Package Signal and Power Integrity Engineer

  • Bonus
  • Equity
  • Benefits

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