Chipset Power Architect, Devices and Services, Silicon
Description For Chipset Power Architect, Devices and Services, Silicon
Google is seeking a Chipset Power Architect to join their Devices and Services Silicon team, focusing on developing custom silicon solutions that power Google's direct-to-consumer products. This role combines advanced hardware engineering with Google's expertise in AI and software to create innovative computing experiences.
The position requires deep expertise in power management and low power design, with responsibilities centered around optimizing Power-Performance-Area (PPA) for Tensor mobile SoCs. You'll lead the definition of power requirements, establish key performance indicators, and work with cross-functional teams to achieve power goals in volume production.
As a Chipset Power Architect, you'll be at the forefront of Google's hardware innovation, working on products that impact millions of users worldwide. The role involves sophisticated technical challenges in SoC power modeling, analysis, and optimization, requiring both technical depth and strategic thinking to balance performance and power efficiency.
The position offers competitive compensation with a base salary range of $183,000-$271,000, plus additional benefits including bonus potential, equity grants, and comprehensive benefits package. This is an opportunity to work with cutting-edge technology while collaborating with world-class engineers and researchers.
The ideal candidate will bring a strong educational background in Electrical Engineering or related fields, with at least 8 years of relevant experience. You should have proven expertise in power management, low power design methodologies, and experience with full product delivery cycles. Knowledge of ASIC design flows and excellent communication skills are essential for success in this cross-functional role.
This position represents a unique opportunity to shape the future of Google's hardware products, working at the intersection of power architecture, performance optimization, and product innovation. You'll be part of a team that pushes boundaries in silicon design while contributing to Google's mission of organizing the world's information and making it universally accessible and useful.
Responsibilities For Chipset Power Architect, Devices and Services, Silicon
- Lead the definition of power requirements for Tensor mobile SoCs
- Define power Key Performance Indicators and SoC/IP-level power goals
- Model system on a chip (SoC) and IP-level power and perform power rollups
- Propose and drive power optimizations throughout the design process
- Drive power-performance trade-off analysis for engineering reviews
Requirements For Chipset Power Architect, Devices and Services, Silicon
- Bachelor's degree in Electrical Engineering or equivalent practical experience
- 8 years of experience in power management or low power design/methodology
- Experience with low power architecture and power optimization techniques
- Experience with full product delivery cycle
- Master's degree or PhD in Electronics or Computer Engineering/Science (preferred)
- Experience with SoC power modeling and analysis (preferred)
- Knowledge of ASIC design flows (preferred)
- Excellent written and verbal communication skills (preferred)
Benefits For Chipset Power Architect, Devices and Services, Silicon
- Bonus
- Equity
- Benefits package
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