CPU Design Verification Engineer
Description For CPU Design Verification Engineer
Google's Server Chip Design team is seeking a CPU Design Verification Engineer to join their Technical Infrastructure team. This role is crucial in building and maintaining Google's cutting-edge data centers and platforms that power all Google services. As a CPU Design Verification Engineer, you'll be responsible for verifying complex digital designs, working with verification components, conducting constrained-random testing, and ensuring verification closure.
The position offers an opportunity to work on some of the most challenging computational problems in the industry, as Google's unique requirements necessitate custom hardware solutions. You'll be part of the team that designs and builds the systems powering the world's largest computing infrastructure. Your work will directly impact millions of Google users through the hardware that goes into Google's data centers.
The role involves collaboration with design and verification engineers on active projects, handling the full lifecycle of verification from planning to coverage closure. You'll work with advanced technologies and methodologies including SystemVerilog, UVM, and formal verification tools. The position requires strong technical skills in digital design verification, RTL-level experience, and familiarity with standard IP components.
This is an excellent opportunity for someone who enjoys working at the intersection of hardware and software, has a strong background in electrical engineering or computer science, and wants to contribute to the infrastructure that powers Google's global services. The role offers the chance to work with cutting-edge technology while solving complex technical challenges that affect millions of users worldwide.
Responsibilities For CPU Design Verification Engineer
- Plan the verification of digital design blocks by understanding the design specification and interact with design engineers
- Create and enhance random verification environments using SystemVerilog and UVM, or formally verify designs with SVA
- Identify and write all types of coverage measures for stimulus and corner-cases
- Debug tests with design engineers to deliver functionally correct design blocks
- Provide close coverage measures to identify verification holes and show progress towards tape-out
Requirements For CPU Design Verification Engineer
- Bachelor's degree in Electrical Engineering or equivalent practical experience
- 3 years of experience creating and using verification components and environments in standard verification methodology
- Experience verifying digital logic at Register-Transfer Level (RTL) level using SystemVerilog or Specman/E for FPGAs or ASICs
- Experience verifying digital systems using standard IP components/interconnects
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