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Design for Testability Engineer, Silicon

Google organizes the world's information and makes it universally accessible and useful, combining AI, Software, and Hardware to create helpful experiences.
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Mid-Level Software Engineer
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5,000+ Employees
5+ years of experience
AI · Enterprise SaaS

Description For Design for Testability Engineer, Silicon

Google is seeking a Design for Testability Engineer to join their Silicon team, focusing on developing custom silicon solutions that power Google's direct-to-consumer products. This role combines hardware engineering with testing expertise, requiring deep knowledge of ASIC design and testing methodologies. The position involves working with cutting-edge technology that impacts millions of users worldwide through Google's hardware experiences.

The ideal candidate will have strong experience in ASIC design for test, including working with silicon lifecycle management and manufacturing processes. They will be responsible for implementing and managing Design for Testing (DFT) verification, pattern generation, and various simulation and analysis tasks. The role requires expertise in ATPG, BIST, and JTAG tools and workflows.

This is an opportunity to work at the intersection of hardware and testing, ensuring the quality and reliability of Google's silicon solutions. The position offers the chance to work with advanced technologies and contribute to the next generation of Google's hardware products. The role combines technical expertise with practical implementation, requiring both theoretical knowledge and hands-on experience in silicon testing and validation.

The position is based in Bengaluru, India, and is part of Google's broader hardware initiative that combines AI, software, and hardware to create innovative user experiences. The successful candidate will join a team that pushes boundaries in silicon development and testing, contributing to Google's mission of organizing the world's information and making it universally accessible and useful.

Last updated 2 days ago

Responsibilities For Design for Testability Engineer, Silicon

  • Work on a team of Design for testing (DFT) verification, Pattern generation, Standard Delay Format (SDF) simulations, Static Timing Analysis (STA) checks
  • Write a Pattern delivery using Automatic Test Pattern Generation (ATPG)
  • Work with Silicon bring-up
  • Work on Yield, Vmin or Return Materials/Merchandise Authorization (RMA) debug and deliver debug patterns. Perform Silicon data analysis

Requirements For Design for Testability Engineer, Silicon

  • Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience
  • 5 years of experience in Application-Specific Integrated Circuit (ASIC) design for test including silicon life cycle through DFT pattern bring-up on Automatic Test Equipment (ATE) and manufacturing
  • Experience with ATPG, Low Value (LV), Built-in self test (BIST) or Joint Test Action Group (JTAG) tool and flow

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