Design Verification Engineer, ASIC
Description For Design Verification Engineer, ASIC
Google is seeking a Design Verification Engineer to join their ASIC team, focusing on developing custom silicon solutions that power Google's direct-to-consumer products. This role combines hardware engineering with software development, requiring expertise in verification methodologies and digital logic.
The position involves working with next-generation configurable Infrastructure IPs, interconnects, and memory subsystems. You'll be responsible for creating and enhancing verification environments using SystemVerilog and UVM, while also developing cross-language tools and methodologies. The role requires strong debugging skills and the ability to work closely with design engineers to ensure functional correctness.
As part of Google's hardware team, you'll contribute to innovations that power products used by millions worldwide. The team combines Google's strengths in AI, Software, and Hardware to create revolutionary computing experiences. Your work will directly impact the performance, efficiency, and integration of Google's hardware products.
The ideal candidate should have a strong background in electrical engineering or computer science, with significant experience in verification methodologies. Knowledge of hardware protocols and SOC verification is highly valued. This role offers the opportunity to work on cutting-edge technology while being part of a team that pushes the boundaries of hardware innovation.
Google offers a collaborative environment with opportunities to shape the future of hardware experiences. The position comes with Google's comprehensive benefits package and the chance to work on products that make a real difference in people's lives. Join a team that's dedicated to making computing faster, seamless, and more powerful through innovative hardware solutions.
Responsibilities For Design Verification Engineer, ASIC
- Plan and execute the verification of the next generation configurable Infrastructure Intellectual Property (IPs), interconnects and memory subsystems
- Create and enhance constrained-random verification environments using SystemVerilog and Universal Verification Methodology (UVM)
- Develop cross language tools and verification methodologies
- Identify and write all types of coverage measures for stimulus and corner-cases
- Debug tests with design engineers to deliver functionally correct blocks and subsystems
Requirements For Design Verification Engineer, ASIC
- Bachelor's degree in Electrical Engineering, Computer Science or equivalent practical experience
- 5 years of experience in coding, developing test methodologies, writing test plans, creating test cases, and debugging
- Experience verifying digital logic at RTL level either using SystemVerilog, C, C++
- Master's degree in Electrical Engineering or Computer Science or equivalent practical experience (preferred)
- Experience with Interconnect Protocols such as AHB, AXI, ACE, CHI, CCIX, CXL (preferred)
- Experience with performance verification of SOC, Pre-Silicon analysis and post-Silicon correlation (preferred)
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